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74ALVC574PW Datenblatt(PDF) 4 Page - NXP Semiconductors |
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74ALVC574PW Datenblatt(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74ALVC574_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 8 November 2007 4 of 17 NXP Semiconductors 74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 74ALVC574 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND CP 001aad095 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aad096 74ALVC574 Transparent top view Q7 D6 D7 Q6 D5 Q5 D4 Q4 D3 Q3 D2 Q2 GND(1) D1 Q1 D0 Q0 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input CP 11 clock input (LOW to HIGH, edge-triggered) OE 1 output enable input (active LOW) Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output VCC 20 supply voltage GND 10 ground (0 V) |
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