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74LVC1G38GV Datenblatt(PDF) 7 Page - NXP Semiconductors |
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74LVC1G38GV Datenblatt(HTML) 7 Page - NXP Semiconductors |
7 / 15 page 74LVC1G38_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 27 August 2007 7 of 15 NXP Semiconductors 74LVC1G38 2-input NAND gate; open drain 12. AC waveforms Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The input (A, B) to output (Y) propagation delays. 001aab719 tPZL tPLZ GND VI VCC VOL VM VM VX Y output A, B input Table 9. Measurement points Supply voltage Input Output VCC VM VM VX 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC VOL + 0.3 V |
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