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SM8760CA Datenblatt(PDF) 5 Page - Nippon Precision Circuits Inc |
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SM8760CA Datenblatt(HTML) 5 Page - Nippon Precision Circuits Inc |
5 / 8 page SM8760CA SEIKO NPC CORPORATION —5 FUNCTIONAL DESCRIPTION Master Clock The SM8760CA master clock can be generated by the crystal oscillator formed by connecting a crystal (funda- mental mode) between XT (pin 1) and XTN (pin 2) as shown in Figure 2. Alternatively, an external master clock can be input directly on XT (pin 1) as shown in Figure 3. If an external clock is input on XT, it is recom- mended that the clock have 50% duty and VDD level voltage amplitude. Note that the input clock amplitude voltage must not exceed the absolute maximum rating, otherwise it may cause the SM8760CA to breakdown. Function Controls The SM8760CA power-down and SS modulation ON/OFF functions are controlled using the PDN and ENS input pins as shown in Table 1. The power-down function is controlled using the PDN input pin. When PDN (pin 3) is “H”, normal operating mode is selected. When PDN is “L”, power-down mode is selected. In power-down mode, the CLKOUT and REFOUT output pins are in a high impedance state. The SS modulation function is controlled using the ENS input pin. When ENS (pin 4) is “H”, the SS modula- tion function is ON, and an SS-modulated clock is output on the CLKOUT pin. When ON, the modulation mode and amplitude is a fixed center spread modulation ± 1.0%. When ENS is “L”, the SS modulation func- tion is OFF. Note. “H” signal represents VDD level, and “L” represents VSS level. Figure 2. Crystal element connection Oscillator Internal Circuits XT (Pin1) XTN (Pin2) C1 C2 C1, C2 = 5 to 33pF Figure 3. External clock input Oscillator Internal Circuits XT (Pin1) XTN (Pin2) Open External Clock Table 1. Function summary PDN (Pin 3) ENS (Pin 4) Power Down Output (Pin 5, Pin 7) SS ON/OFF SS Mode SS Modulation [%] HH OFF Clock out ON Center spread ± 1.0 H L OFF − 0.0 LH ON Hi-Z −− − LL |
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Ähnliche Beschreibung - SM8760CA |
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