TC59LM913AMG-50 datasheet(9/46 Pages) TOSHIBA

Teilenummer	TC59LM913AMG-50

Bauteilbeschribung	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

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Hersteller	TOSHIBA [Toshiba Semiconductor]

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9 / 46 page

TC59LM913AMG-50

2005-11-08

9/46

Rev 1.1

AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)

SYMBOL

PARAMETER

MIN

MAX

UNIT

NOTES

tLZ

Data-out Low Impedance Time from CLK

−0.65



3,6,8

tHZ

Data-out High Impedance Time from CLK



0.65

3,7,8

tQSLZ

DQS-out Low Impedance Time from CLK

−0.65



3,6,8

tQSHZ

DQS-out High Impedance Time from CLK

−0.65

0.65

3,7,8

tQPDH

Last output to PD High Hold Time

0



tPDEX

Power Down Exit Time

0.9



3

tT

Input Transition Time

0.1

1

tFPDL

PD

Low Input Window for Self-Refresh Entry

−0.5 × tCK

5

ns

3

tREFI

Auto-Refresh Average Interval

0.4

3.9

5

tPAUSE

Pause Time after Power-up

200



µs

IRC

Random Read/Write Cycle Time

(applicable to same bank)

5



IRCD

RDA/WRA to LAL Command Input Delay

(applicable to same bank)

1

IRAS

LAL to RDA/WRA Command Input Delay

(applicable to same bank)

4



IRBD

Random Bank Access Delay

(applicable to other bank)

2



BL = 2

2



IRWD

LAL following RDA to WRA Delay

(applicable to other bank)

BL = 4

3



IWRD

LAL following WRA to RDA Delay

(applicable to other bank)

1



IRSC

Mode Register Set Cycle Time

CL = 3

5



IPD

PD

Low to Inactive State of Input Buffer



1

IPDA

PD

High to Active State of Input Buffer



1

IPDV

Power down mode valid from REF command

18



IREFC

Auto-Refresh Cycle Time

18



ICKD

REF Command to Clock Input Disable at Self-Refresh Entry

16



ILOCK

DLL Lock-on Time (applicable to RDA command)

200



cycle

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