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TC74HC40103AF Datenblatt(PDF) 11 Page - Toshiba Semiconductor |
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TC74HC40103AF Datenblatt(HTML) 11 Page - Toshiba Semiconductor |
11 / 14 page TC74HC40102,40103AP/AF 2007-10-01 11 Example of Typical Application Programmable Divide-by-N Counter Parallel Carry Cascading (Note) Note: At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival. Therefore, take gate form TC74HC32A or the like, not form C0 output at the rear stage directly. Programmable Timer (Note) Note: The above formula dose not take into account the phase of ck input. Therefore, the real pulse width is the distance between the above formula-1/fIN to the above formula. (Note) |
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