Datenblatt-Suchmaschine für elektronische Bauteile |
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74AC138TTR Datenblatt(PDF) 1 Page - STMicroelectronics |
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74AC138TTR Datenblatt(HTML) 1 Page - STMicroelectronics |
1 / 10 page 1/10 April 2001 s HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC138 is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high. Tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74AC138 3 TO 8 LINE DECODER (INVERTING) PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP 74AC138B SOP 74AC138M 74AC138MTR TSSOP 74AC138TTR TSSOP DIP SOP |
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