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AM486DE2 Datenblatt(PDF) 6 Page - Advanced Micro Devices

Teilenummer AM486DE2
Bauteilbeschribung  8-Kbyte Write-Through Embedded Microprocessor
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Hersteller  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM486DE2 Datenblatt(HTML) 6 Page - Advanced Micro Devices

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Am486DE2 Microprocessor
FIGURES
Figure 1
Entering Stop Grant State ........................................................................................................ 19
Figure 2
Stop Clock State Machine ........................................................................................................ 21
Figure 3
Recognition of Inputs when Exiting Stop Grant State .............................................................. 21
Figure 4
Basic SMI Interrupt Service...................................................................................................... 23
Figure 5
Basic SMI Hardware Interface ................................................................................................. 23
Figure 6
SMI Timing for Servicing an I/O Trap ....................................................................................... 24
Figure 7
SMIACT Timing ........................................................................................................................ 25
Figure 8
Redirecting System Memory Address to SMRAM ................................................................... 25
Figure 9
Transition to and from SMM ..................................................................................................... 27
Figure 10 Auto Halt Restart Register Offset ............................................................................................. 30
Figure 11 I/O Instruction Restart Register Offset ..................................................................................... 30
Figure 12 SMM Base Slot Offset .............................................................................................................. 31
Figure 13 SRAM Usage ........................................................................................................................... 31
Figure 14 SMRAM Location ..................................................................................................................... 32
Figure 15 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with
Caching Enabled During SMM ................................................................................................. 32
Figure 16 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with
Caching
Enabled During SMM ................................................................................................. 33
Figure 17 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode with
Caching
Disabled During SMM ................................................................................................ 33
Figure 18 CLK Waveforms ....................................................................................................................... 43
Figure 19 Output Valid Delay Timing ....................................................................................................... 44
Figure 20 Maximum Float Delay Timing................................................................................................... 44
Figure 21 PCHK Valid Delay Timing ........................................................................................................ 45
Figure 22 Input Setup and Hold Timing.................................................................................................... 46
Figure 23 RDY and BRDY Input Setup and Hold Timing ......................................................................... 47
Figure 24 TCK Waveforms ....................................................................................................................... 47
Figure 25 Test Signal Timing Diagram ..................................................................................................... 48
Figure 26 Heat Sink Dimensions .............................................................................................................. 49
TABLES
Table 1
EADS Sample Time ................................................................................................................. 13
Table 2
Pin State During Stop Grant Bus State .................................................................................... 19
Table 3
SMRAM State Save Map ......................................................................................................... 26
Table 4
SMM Initial CPU Core Register Settings.................................................................................. 28
Table 5
Segment Register Initial States ................................................................................................ 28
Table 6
System Management Mode Revision Identifier........................................................................ 29
Table 7
SMM Revision Identifier Bit Definitions .................................................................................... 29
Table 8
Auto Halt Restart Configuration ............................................................................................... 30
Table 9
I/O Trap Word Configuration .................................................................................................... 30
Table 10
Test Register (TR4).................................................................................................................. 36
Table 11
Test Register (TR5).................................................................................................................. 36
Table 12
Am486DE2 Microprocessor Functional Differences ................................................................ 37
Table 13
CPU ID Codes.......................................................................................................................... 37
Table 14
CPUID Instruction Description ................................................................................................. 38
Table 15
Thermal Resistance (°C/W)
θJC and θJA for the Am486DE2 in 168-Pin PGA Package .......... 49
Table 16
Maximum TA at Various Airflows in
°C ..................................................................................... 49


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