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OP27 Datenblatt(PDF) 4 Page - Analog Devices

Teilenummer OP27
Bauteilbeschribung  Low Noise, Precision Operational Amplifier
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OP27
Rev. F | Page 4 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP27A/E
OP27/G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
INPUT OFFSET VOLTAGE1
VOS
10
25
30
100
μV
LONG-TERM VOS STABILITY2, 3
VOS/Time
0.2
1.0
0.4
2.0
μV/MO
INPUT OFFSET CURRENT
IOS
7
35
12
75
nA
INPUT BIAS CURRENT
IB
±10
±40
±15
±80
nA
INPUT NOISE VOLTAGE3, 4
en p-p
0.1 Hz to 10 Hz
0.08
0.18
0.09
0.25
μV p-p
INPUT NOISE
en
fO = 10 Hz
3.5
5.5
3.8
8.0
nV/√Hz
Voltage Density3
fO = 30 Hz
3.1
4.5
3.3
5.6
nV/√Hz
fO = 1000 Hz
3.0
3.8
3.2
4.5
nV/√Hz
INPUT NOISE
in
fO = 10 Hz
1.7
4.0
1.7
pA/√Hz
Current Density3
fO = 30 Hz
1.0
2.3
1.0
pA/√Hz
fO = 1000 Hz
0.4
0.6
0.4
0.6
pA/√Hz
INPUT RESISTANCE
Differential Mode5
RIN
1.3
6
0.7
4
Common Mode
RINCM
3
2
INPUT VOLTAGE RANGE
IVR
±11.0
±12.3
±11.0
±12.3
V
COMMON-MODE REJECTION RATIO
CMRR
VCM = ±11 V
114
126
100
120
dB
POWER SUPPLY REJECTION RATIO
PSRR
VS = ±4 V to ±18 V
1
10
2
20
μV/V
LARGE SIGNAL VOLTAGE GAIN
AVO
RL ≥ 2 k Ω, VO = ±10 V
1000
1800
700
1500
V/
mV
RL ≥ 600 Ω, VO = ±10 V
800
1500
600
1500
V/
mV
OUTPUT VOLTAGE SWING
VO
RL ≥ 2 k Ω
±12.0
±13.8
±11.5
±13.5
V
RL ≥ 600 Ω
±10.0
±11.5
±10.0
±11.5
V
SLEW RATE6
SR
RL ≥ 2 kΩ
1.7
2.8
1.7
2.8
V/μs
GAIN BANDWIDTH PRODUCT6
GBW
5.0
8.0
5.0
8.0
MHz
OPEN-LOOP OUTPUT RESISTANCE
RO
VO = 0, IO = 0
70
70
Ω
POWER CONSUMPTION
Pd
VO
90
140
100
170
mW
OFFSET ADJUSTMENT RANGE
RP = 10 kΩ
±4.0
±4.0
mV
1 Input offset voltage measurements are performed approximately 0.5 seconds after application of power. A/E grades guaranteed fully warmed up.
2 Long-term input offset voltage stability refers to the average trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 days are typically 2.5 μV. Refer to the Typical Performance Characteristics section.
3 Sample tested.
4 See voltage noise test circuit (Figure 31).
5 Guaranteed by input bias current.
6 Guaranteed by design.


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