Datenblatt-Suchmaschine für elektronische Bauteile |
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CD4081BMS Datenblatt(PDF) 1 Page - Intersil Corporation |
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CD4081BMS Datenblatt(HTML) 1 Page - Intersil Corporation |
1 / 10 page January 1993 7-433 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4073BMS, CD4081BMS CD4082BMS CMOS AND Gate Pinout CD4073BMS TOP VIEW CD4081BMS TOP VIEW CD4082BMS TOP VIEW A B D E F K = D • E • F VSS VDD G H I L = G • H • I J = A • B • C C 1 2 3 4 5 6 7 14 13 12 11 10 9 8 A B J = A • B K = C • D C D VSS VDD H G M = G • H L = E • F F E 1 2 3 4 5 6 7 14 13 12 11 10 9 8 J = A • B • C • D D C B A NC VSS VDD K = E • F • G • H H G F E NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 NC = NO CONNECTION Features • High-Voltage Types (20V Rating) • CD4073BMS Triple 3-Input AND Gate • CD4081BMS Quad 2-Input AND Gate • CD4082BMS Dual 4-Input AND Gate • Medium Speed Operation: - tPLH, tPHL = 60ns (typ) at VDD = 10V • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1 µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Description CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates. The CD4073BMS, CD4081BMS and CD4082BMS are supplied in these 14 lead outline packages: Braze Seal DIP *H4Q †H4H Frit Seal DIP *H1B Ceramic Flatpack *H3W *CD4073B, CD4081B †CD4082B File Number 3324 |
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