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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ADSP-BF538BBCZ-4F8 Datenblatt(PDF) 5 Page - Analog Devices |
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ADSP-BF538BBCZ-4F8 Datenblatt(HTML) 5 Page - Analog Devices |
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5 / 56 page  ADSP-BF538/ADSP-BF538F Rev. 0 | Page 5 of 56 | May 2007 The address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C style indexed stack manipulation). Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. In addition, multiple L1 memory blocks are provided, offering a configurable mix of SRAM and cache. The Memory Manage- ment Unit (MMU) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. The architecture provides three modes of operation: User mode, Supervisor mode, and Emulation mode. User mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. The Blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support a limited multi-issue capability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. The Blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations. MEMORY ARCHITECTURE The ADSP-BF538/ADSP-BF538F processors view memory as a single unified 4G byte address space, using 32-bit addresses. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/per- formance balance of some very fast, low latency on-chip memory as cache or SRAM, and larger, lower cost and perfor- mance off-chip memory systems. See Figure 3. The L1 memory system is the primary highest performance memory available to the Blackfin processor. The off-chip mem- ory system, accessed through the External Bus Interface Unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of physical memory. The memory DMA controllers provide high bandwidth data movement capability. They can perform block transfers of code or data between the internal memory and the external memory spaces. Internal (On-chip) Memory The ADSP-BF538/ADSP-BF538F processors have three blocks of on-chip memory providing high bandwidth access to the core. The first is the L1 instruction memory, consisting of 80K bytes SRAM, of which 16K bytes can be configured as a four way set- associative cache. This memory is accessed at full processor speed. The second on-chip memory block is the L1 data memory, con- sisting of two banks of up to 32K bytes each. Each memory bank is configurable, offering both two-way set-associative cache and SRAM functionality. This memory block is accessed at full pro- cessor speed. The third memory block is a 4K byte scratchpad SRAM which runs at the same speed as the L1 memories, but is only accessible as data SRAM and cannot be configured as cache memory. Figure 3. ADSP-BF538/ADSP-BF538F Internal/External Memory Map RESERVED CORE MMR REGISTERS (2M BYTE) RESERVED SCRATCHPAD SRAM (4K BYTE) INSTRUCTION SRAM (64K BYTE) SYSTEM MMR REGISTERS (2M BYTE) RESERVED RESERVED DATA BANK B SRAM/CACHE (16K BYTE) DATA BANK B SRAM (16K BYTE) DATA BANK A SRAM/CACHE (16K BYTE) ASYNC MEMORY BANK 3 (1M BYTE) OR ON-CHIP FLASH (ADSP-BF538F ONLY) ASYNC MEMORY BANK 2 (1M BYTE) OR ON-CHIP FLASH (ADSP-BF538F ONLY) ASYNC MEMORY BANK 1 (1M BYTE) OR ON-CHIP FLASH (ADSP-BF538F ONLY) ASYNC MEMORY BANK 0 (1M BYTE) OR ON -CHIP FLASH (ADSP-BF538F ONLY) SDRAMMEMORY(16MBYTE TO 128M BYTE) INSTRUCTION SRAM/CACHE (16K BYTE) 0xFFFF FFFF 0xFFE0 0000 0xFFB0 0000 0xFFA1 4000 0xFFA1 0000 0xFF90 8000 0xFF90 4000 0xFF80 8000 0xFF80 4000 0xEF00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xFFC0 0000 0xFFB0 1000 0xFFA0 0000 RESERVED RESERVED DATA BANK A SRAM (16K BYTE) 0xFF90 0000 0xFF80 0000 RESERVED |
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