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ADSP-BF538BBCZ-4F8 Datenblatt(PDF) 9 Page - Analog Devices

Teilenummer ADSP-BF538BBCZ-4F8
Bauteilbeschribung  Blackfin짰 Embedded Processor
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ADSP-BF538BBCZ-4F8 Datenblatt(HTML) 9 Page - Analog Devices

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ADSP-BF538/ADSP-BF538F
Rev. 0
|
Page 9 of 56
|
May 2007
• SIC interrupt mask registers (SIC_IMASKx) – These regis-
ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servic-
ing the event.
• SIC interrupt status registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
• SIC interrupt wakeup enable registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
mation, see Dynamic Power Management on Page 13.)
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND
register contents are monitored by the SICs as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF538/ADSP-BF538F processors have two, inde-
pendent DMA controllers that support automated data transfers
with minimal overhead for the processor core. DMA transfers
can occur between the processor internal memories and any of
its DMA capable peripherals. Additionally, DMA transfers can
be accomplished between any of the DMA capable peripherals
and external devices connected to the external memory inter-
faces, including the SDRAM controller and the asynchronous
memory controller. DMA capable peripherals include the
SPORTs, SPI ports, UARTs, and PPI. Each individual DMA
capable peripheral has at least one dedicated DMA channel.
The DMA controllers support both 1-dimensional (1-D) and 2-
dimensional (2-D) DMA transfers. DMA transfer initialization
can be implemented from registers or from sets of parameters
called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
deinterleaved on the fly.
Examples of DMA types supported by the processor DMA con-
troller include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
four memory DMA channels provided for transfers between the
various memories of the ADSP-BF538/ADSP-BF538F proces-
sor’s systems. This enables transfers of blocks of data between
any of the memories—including external SDRAM, ROM,
SRAM, and flash memory—with minimal processor interven-
tion. Memory DMA transfers can be controlled by a very
flexible descriptor based methodology or by a standard register
based autobuffer mechanism.
REAL TIME CLOCK
The ADSP-BF538/ADSP-BF538F processor’s real time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 kHz crystal external to the processor. The RTC periph-
eral has dedicated power supply pins so that it can remain
powered up and clocked even when the rest of the processors
are in a low power state. The RTC provides several programma-
ble interrupt options, including interrupt per second, minute,
hour, or day clock ticks, interrupt on programmable stopwatch
countdown, or interrupt at a programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a 24
hour counter, and a 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the ADSP-
BF538/ADSP-BF538F processor from sleep mode upon genera-
tion of any RTC wakeup event. Additionally, an RTC wakeup
event can wake up the processor from deep sleep mode and
wake up the on-chip internal voltage regulator from the pow-
ered down hibernate state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.


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