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TSB83AA23

SLLS787 – AUGUST 2007

The TSB83AA23 PHY section provides the digital and analog transceiver functions needed to implement a

three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line

transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining

connection status, for initialization and arbitration, and for packet reception and transmission.

The TSB83AA23 is powered by multiple voltage supplies, 3.3-V supplies for I/O and the LLC section, and a core

voltage supply for the PHY section. The core voltage supply is supplied to the PLLVDD_CORE and

DVDD_CORE terminals in accordance with the requirements in the recommended operating conditions. The

PLLVDD_CORE terminals must be separated from the DVDD_CORE terminals, the PLLVDD_CORE terminals

are decoupled with 1-

μF and smaller decoupling capacitors, and the DVDD_CORE terminals separately

decoupled with 1-

μF and smaller decoupling capacitors. The separation between DVDD_CORE and

PLLVDD_CORE can be implemented by separate power-supply rails, or by a single power-supply rail, where the

DVDD_CORE and PLLVDD_CORE are separated by a filter network to keep noise from the PLLVDD_CORE

supply. In addition, REG_EN must be asserted low to enable the internal voltage regulator for the LLC section. If

REG_EN is not pulled low, the a 1.8-V power rail must be applied to the REG18 pins.

The TSB83AA23 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external

clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference

signal provides the clock signals that control transmission of the outbound encoded information. The power-down

(PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and

transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbps (referred to as S100, S200, S400, S400B, or

S800 speed, respectively) as the outbound information stream.

To ensure that the TSB83AA23 conforms to the IEEE Std 1394b-2002 standard, the BMODE terminal must be

asserted.

NOTE:

The BMODE terminal does not select the cable-interface mode of operation. The

BMODE terminal selects the internal PHY section-LLC section interface mode of

operation and affects the arbitration modes on the cable. BMODE must be pulled high

during normal operation.

The cable interface can follow either the IEEE Std 1394a-2000 protocol or the IEEE Std 1394b-2002 protocol on

all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When

any of the ports are connected to an IEEE Std 1394a-2000-compliant device, the cable interface on that port

operates in the IEEE Std 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a

bilingual port is connected to an IEEE Std 1394b-2002-compliant node, the cable interface on that port operates

per the IEEE Std 1394b-2002 standard at S400B or S800 speed. The TSB83AA23 automatically determines the

correct cable interface connection method for the bilingual ports.

To operate a port as an IEEE Std 1394b-2002 bilingual port, the data-strobe-only terminal for the port (DS0 or

DS1) must be pulled to ground through a 1-k

Ω resistor. The port must be operated in the IEEE Std 1394b-2002

bilingual mode when an IEEE Std 1394b-2002 bilingual or an IEEE Std 1394b-2002 Beta-only connector is

connected to the port. To operate the port as an IEEE Std 1394a-2000-only port, the data-strobe-only terminal

data-strobe-only mode is if the port is connected to an IEEE Std 1394a-2000 connector (either 6 pin, which is

recommended, or 4 pin). This mode is provided to ensure that IEEE Std 1394b-2002 signaling is never sent

across an IEEE Std 1394a-2000 cable.

During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams by the PHY section and

sent to the link-layer controller (LLC) section. The received data is also transmitted (repeated) on the other

connected and active cable ports.

Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators

to

monitor

the

line

states

during

initialization

and

arbitration

when

connected

to

an

IEEE

Std

1394a-2000-compliant device. The outputs of these comparators are used by the internal logic to determine the

arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this

common-mode voltage is used during IEEE Std 1394a-2000-mode arbitration and sets the speed of the next

packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the

TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage.

Copyright © 2007, Texas Instruments Incorporated

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