Datenblatt-Suchmaschine für elektronische Bauteile |
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ADSP-BF538BBCZ-4F8 Datenblatt(PDF) 2 Page - Analog Devices |
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ADSP-BF538BBCZ-4F8 Datenblatt(HTML) 2 Page - Analog Devices |
2 / 56 page Rev. A | Page 2 of 56 | January 2008 ADSP-BF538/ADSP-BF538F TABLE OF CONTENTS General Description ................................................. 3 Low Power Architecture ......................................... 3 System Integration ................................................ 3 ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3 Blackfin Processor Core .......................................... 4 Memory Architecture ............................................ 5 DMA Controllers .................................................. 9 Real-Time Clock ................................................... 9 Watchdog Timer ................................................ 10 Timers ............................................................. 10 Serial Ports (SPORTs) .......................................... 10 Serial Peripheral Interface (SPI) Ports ...................... 10 2-Wire Interface ................................................. 11 UART Ports ...................................................... 11 General-Purpose Ports ......................................... 11 Parallel Peripheral Interface ................................... 12 Controller Area Network (CAN) Interface ................ 13 Dynamic Power Management ................................ 13 Voltage Regulation .............................................. 14 Booting Modes ................................................... 16 Instruction Set Description ................................... 16 Development Tools ............................................. 17 Designing an Emulator Compatible Processor Board ... 18 Pin Descriptions .................................................... 19 Specifications ........................................................ 23 Operating Conditions .......................................... 23 Electrical Characteristics ....................................... 24 Absolute Maximum Ratings ................................... 25 Package Information ............................................ 25 ESD Sensitivity ................................................... 25 Timing Specifications ........................................... 26 Clock and Reset Timing ..................................... 27 Asynchronous Memory Read Cycle Timing ............ 28 Asynchronous Memory Write Cycle Timing ........... 30 SDRAM Interface Timing .................................. 32 External Port Bus Request and Grant Cycle Timing .. 33 Parallel Peripheral Interface Timing ...................... 35 Serial Port Timing ............................................ 38 Serial Peripheral Interface Ports—Master Timing ..... 41 Serial Peripheral Interface Ports—Slave Timing ....... 42 General-Purpose Port Timing ............................. 43 Timer Cycle Timing .......................................... 44 JTAG Test And Emulation Port Timing ................. 45 Output Drive Currents ......................................... 46 Power Dissipation ............................................... 48 Test Conditions .................................................. 48 Thermal Characteristics ........................................ 51 316-Ball CSP_BGA Ball Assignments .......................... 52 Outline Dimensions ................................................ 55 Surface-Mount Design .......................................... 56 Ordering Guide ..................................................... 56 REVISION HISTORY 1/08—Rev. 0 to Rev. A Identifying pins CANRX and PC4 as 5 V-tolerant when config- ured as an input and an open-drain when configured as an output. |
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