Datenblatt-Suchmaschine für elektronische Bauteile |
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LM2507SQ Datenblatt(PDF) 9 Page - National Semiconductor (TI) |
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LM2507SQ Datenblatt(HTML) 9 Page - National Semiconductor (TI) |
9 / 22 page Functional Description (Continued) READ TRANSACTION The READ transaction is fixed in length. It consists of four sections. In the first section the Master sends a READ Command to the slave. This command is sent in a single MC cycle (2 edges) and uses a similar format to the 1st cycle of the WRITE transaction. The MD0 line carries the Start bit (Low) and the A/D (Address/Data) bit. The MD1 line carries the R/W* bit (High for reads) and the CS1/2 bit. The Slave has an optional feature selected by the IDR pin. If IDR is pulled high, as soon as the READ Command is detected by the Slave, it issues two reads to the peripheral device. If IDR is pulled low, the Slave only issues one read. This feature allows a common behavior from the host side regardless of whether the MPL link is used. Since the Master mode device requires a dummy READ (which returns all zeros) to initiate the remote side read, and then another READ after the INTR signal is received, the remote side can be programmed to behave in exactly the same way. Com- mon driver software can be created that would be transpar- ent to the use of the MPL link. In the second section (TA’) the MD lines are turned around, such that the Master becomes the receiver and Slave be- comes the transmitter. The Slave must drive the MD lines High by the 14th clock edge. It may then idle the line at the Logic High state or drive the line Low (Start bit) to indicate that read data transmission is starting. This ensures that the MD lines are a stable High state and that the High-to-Low transition of the "Start" bit is seen by the Master. Figure 9 illustrates a READ_Command and TA’ with IDR (Insert Dummy Read) = L. If the IDR = H, then the Bus undetermined state is longer (10 additional MC cycles) to allow for the dummy read cycle on the Slave output to occur. The third section is consists of the transfer of the read data from the Slave to the Master. Note that the READ_Data operates on single-edge clocking (Rising Edge ONLY). Therefore the back channel data signaling rate is 1⁄2 of the forward channel (Master-to-Slave direction). When the Slave is ready to transmit data back to the Master it drives the MD lines Low to indicate start of read data, followed by 8 MC cycles of the actual read data payload. The fourth and final section (TA") occurs after the read data has been transferred from the Slave to the Master. In the fourth section the MD lines are again turned around, such that the Master becomes the transmitter and the Slave be- comes the receiver. The Slave drives the MD lines High for 1 bit and then turns off. The MD lines are off momentarily to avoid driver contention. The Master then drives the MD line High for 1 bit time and then idles the bus until the next transaction is sent. The Master watches the MD line for the READ Start Bit. When this transition (High to Low) is detected it then selects the proper strobe to clock in the data with maximum margin. 20186007 FIGURE 8. 16-bit CPU WRITE Transaction 20186008 FIGURE 9. READ_Command and TA’ www.national.com 9 |
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