KM416S1120DT-GF7 datasheet(4/43 Pages) SAMSUNG

Teilenummer	KM416S1120DT-GF7

Bauteilbeschribung	512K x 16bit x 2 Banks Synchronous DRAM LVTTL

Download	43 Pages

Scroll/Zoom	100%

Hersteller	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

Logo

4 / 43 page

KM416S1120D

CMOS SDRAM

- 4 -

Rev. 1.4 (Jun. 1999)

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

VSSQ

DQ6

DQ7

VDDQ

LDQM

WE

CAS

RAS

CS

BA

A10/AP

A0

A1

A2

A3

VDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

PIN CONFIGURATION (TOP VIEW)

VSS

DQ15

DQ14

VSSQ

DQ13

DQ12

VDDQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VDDQ

N.C/RFU

UDQM

CLK

CKE

N.C

A9

A8

A7

A6

A5

A4

VSS

50PIN TSOP (II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

PIN FUNCTION DESCRIPTION

Name

Input Function

CLK

System Clock

Active on the positive going edge to sample all inputs.

CS

Chip Select

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and L(U)DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A10/AP

Address

Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, column address : CA0 ~ CA7

BA

Bank Select Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE

Write Enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

L(U)DQM

Data Input/Output Mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ 15

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power Supply/Ground

Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data Output Power/Ground

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

N.C/RFU

No Connection/

Reserved for Future Use

This pin is recommended to be left No Connection on the device.

Ähnliche Beschreibung - KM416S1120DT-GF7

Hersteller	Teilenummer	Datenblatt	Bauteilbeschribung
List of Unclassifed Man...	KM416S1120D	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL
Samsung semiconductor	K4S161622D	1Mb / 41P	512K x 16Bit x 2 Banks Synchronous DRAM
	KM416S1021C	78Kb / 8P	512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
	K4S281632B	108Kb / 10P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632M	87Kb / 10P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030B	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S561632A	127Kb / 10P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632C	47Kb / 9P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632D	112Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S561632D-TC75000	64Kb / 11P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

More results

KM416S1120DT-GF7 Datenblatt(PDF) 4 Page - Samsung semiconductor

KM416S1120DT-GF7 Datenblatt(HTML) 4 Page - Samsung semiconductor

Ähnliche Teilenummer - KM416S1120DT-GF7

Ähnliche Beschreibung - KM416S1120DT-GF7

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datenblatt Download

Link URL