Datenblatt-Suchmaschine für elektronische Bauteile |
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ST10 Datenblatt(PDF) 7 Page - STMicroelectronics |
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ST10 Datenblatt(HTML) 7 Page - STMicroelectronics |
7 / 58 page ST10F163 7/58 P4.0 – P4.7 23-26 29-32 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direc- tion bits. For a pin configured as input, the output driver is put into high-imped- ance state. For external bus configuration, Port 4 can be used to output the segment address lines: 23 O P4.0 A16 Least Significant Segment Addr. Line ... ... ... ... ... 26 O P4.3 A19 Segment Address Line 29 O P4.4 A20 Segment Address Line O SSPCE1 SSP Chip Enable Line 1 30 O P4.5 A21 Segment Address Line O SSPCE0 SSP Chip Enable Line 0 31 O P4.6 A22 Segment Address Line I/O SSPDAT SSP Data Input/Output Line 32 O P4.7 A23 Most Significant Segment Addr. Line O SSPCLK SSP Clock Output Line RD 33 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/WRL 34 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. READY 35 I Ready Input. When the READY function is enabled, a high level at this pin dur- ing an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ALE 36 O Address Latch Enable Output. Can be used for latching the address into exter- nal memory or an address latch in the multiplexed bus modes. EA 37 I External Access Enable pin. A low level at this pin during and after Reset forces the device to begin instruction execution out of external memory. A high level forces execution out of the internal flash EPROM. PORT0: P0L.0-P0L.7 P0H.0-P0H.7 41-48 51-58 I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Table 1 : Pin definitions and functions (continued) Symbol Pin Number( TQFP ) Input (I) Output (O) Function Demultiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15 Multiplexed bus modes Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15 |
Ähnliche Teilenummer - ST10 |
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Ähnliche Beschreibung - ST10 |
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