CD74HC40103Q1

HIGHSPEED CMOS LOGIC

8STAGE SYNCHRONOUS DOWN COUNTER

SCLS547A − OCTOBER 2003 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

Mode

− Standard Outputs ... 10 LSTTL Loads

− Bus Driver Outputs ... 15 LSTTL Loads

Times

LSTTL Logic ICs

description/ordering information

The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage

synchronous down counter with a single output, which is active when the internal count is zero. The device

contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for

clearing the counter to its maximum count, and for presetting the counter either synchronously or

asynchronously. All control inputs and the terminal count (TC) output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)

output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches

zero, if TE is low, and remains low for one full clock period.

When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on

the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input

is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,

or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset

any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 125°C

SOIC − M

Tape and reel

CD74HC40103QM96Q1

HC40103Q

† For the most current package and ordering information, see the Package Option Addendum at the

end of this document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

M PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CP

MR

TE

P0

P1

P2

P3

GND

PE (SYNC)

TC

P7

P6

P5

P4

PL (ASYNC)