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ST62T28C Datenblatt(PDF) 11 Page - STMicroelectronics |
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ST62T28C Datenblatt(HTML) 11 Page - STMicroelectronics |
11 / 84 page 11/84 ST62T28C/E28C MEMORY MAP (Cont’d) 1.3.6 Data RAM Bank Register (DRBR) Address: CBh — Write only Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 3 - DRBR3. This bit, when set, selects RAM Page 1. Bit 2.0 These bits are not used. The selection of the bank is made by programming the Data RAM Bank Switch register (DRBR regis- ter) located at address CBh of the Data Space ac- cording to Table 1. No more than one bank should be set at a time. The DRBR register can be addressed like a RAM Data Space location at the address CBh; never- theless it is a write only register that cannot be ac- cessed with single-bit operations. This register is used to select the desired 64-byte RAM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address). This register is not cleared during the MCU initiali- zation, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional informa- tion. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes: Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing in- terrupt service routine, as the service routine can- not save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. In DRBR Register, only 1 bit must be set. Other- wise two or more pages are enabled in parallel, producing errors. Table 5. Data RAM Bank Register Set-up 70 - - - DRBR4 DRBR3 - - - DRBR ST62T28C/E28C 00h None 01h Reserved 02h Reserved 08h RAM Page 1 10h RAM Page 2 other Reserved 11 |
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