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AD8158ACPZ Datenblatt(PDF) 8 Page - Analog Devices

Teilenummer AD8158ACPZ
Bauteilbeschribung  6.5 Gbps Quad Buffer Mux/Demux
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Direct Link  http://www.analog.com
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AD8158ACPZ Datenblatt(HTML) 8 Page - Analog Devices

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AD8158
Rev. 0 | Page 8 of 36
Pin No.
Mnemonic
Type
Description
95
SEL3
Control1
Lane 3 A/B Switch Control
96
SEL2
Control1
Lane 2 A/B Switch Control
97
SEL1
Control1
Lane 1 A/B Switch Control
98
SEL0
Control1
Lane 0 A/B Switch Control
99
BICAST
Control1
Enable Bicast Mode for Port A and Port B Outputs
100
SEL4G
Control1
Set Transmitter for Low Speed PE
1 Logic level of control pins referred to DVCC.
2 EQ control pins (EQ_A0, EQ_A1, EQ_B0, EQ_B1, EQ_C0, EQ_C1) require 5 kΩ in series when DVCC > VCC.


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