ADM1186

Rev. 0 | Page 8 of 28

Pin No.

ADM1186-1

ADM1186-2

Mnemonic

Description

12

9

DLY_EN_OUT4

Timing Input. The capacitor connected to this input sets the time delay between VIN3

coming into compliance and OUT4 being asserted high during a power-up sequence.

During a power-down sequence, this input sets the time delay between OUT4 being

asserted low and OUT3 being asserted low.

13

10

BLANK_DLY

Timing Input. The capacitor connected to this input sets the blanking time. This is the

time allowed between OUTx being asserted and VINx coming into compliance; otherwise,

the SET FAULT state is entered.

14

SEQ_DONE

power-up sequence is complete, SEQ_DONE is asserted high. During a power-down

sequence, the pin remains asserted until the time delay set by DLY_EN_OUT1 has

elapsed. When a fault occurs, this pin is asserted low.

15

11

PWRGD

state of this pin is a logical AND function of the UV threshold state of the VINx pins. When

the voltage on all VINx inputs exceeds 0.6 V, PWRGD is asserted. This output is driven low

if the voltage on any VINx pin is below 0.6 V.

16

12

OUT4

power-up sequence, this output is asserted high after the time delay set by the capacitor

on DLY_EN_OUT4 has elapsed. The output is asserted low immediately after a power-

down sequence has been initiated.

17

13

OUT3

power-up sequence, this output is asserted high after the time delay set by the capacitor

on DLY_EN_OUT3 has elapsed. During a power-down sequence, the output is asserted

low after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed.

18

14

OUT2

power-up sequence, this output is asserted high after the time delay set by the capacitor

on DLY_EN_OUT2 has elapsed. During a power-down sequence, the output is asserted

low after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed.

19

15

OUT1

power-up sequence, this output is asserted high after the time delay set by the capacitor

on DLY_EN_OUT1 has elapsed (ADM1186-1) or immediately after a rising edge on

UP/DOWN (ADM1186-2). During a power-down sequence, the output is asserted low

after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed.

20

16

VCC

Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.