Datenblatt-Suchmaschine für elektronische Bauteile
Selected language     German  ▼

Delete All
ON OFF
ALLDATASHEETDE.COM

X  

Preview PDF Download HTML

STLC5460 Datenblatt(PDF) 14 Page - STMicroelectronics

Teile-Nr. STLC5460
Beschreibung  LINE CARD INTERFACE CONTROLLER
Download  54 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Hersteller  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5460 Datenblatt(HTML) 14 Page - STMicroelectronics

STLC5460 Datenblatt HTML 10Page - STMicroelectronics STLC5460 Datenblatt HTML 11Page - STMicroelectronics STLC5460 Datenblatt HTML 12Page - STMicroelectronics STLC5460 Datenblatt HTML 13Page - STMicroelectronics STLC5460 Datenblatt HTML 14Page - STMicroelectronics STLC5460 Datenblatt HTML 15Page - STMicroelectronics STLC5460 Datenblatt HTML 16Page - STMicroelectronics STLC5460 Datenblatt HTML 17Page - STMicroelectronics STLC5460 Datenblatt HTML 18Page - STMicroelectronics
Zoom Inzoom in Zoom Outzoom out
 14 / 54 page
background image
M0D
Multiplex 0 Disable.
M0D = 1. Multiplex 0 output is at high impedance continuously,
multiplex 0 input is forced to ”1”, if it is GCI.
TIMD
Timer Monitor Channel Disabled.
TIMD = 1. The timer 1ms is disabled for each Transmit Monitor Channel.
ISPM
Input Sampling Multiplex.
ISPM = 0. The input bit is sampled at half bit time.
ISPM = 1. The input bit is sampled at 3/4 bit time.
MOD
Multiplex Open Drain.
MOD = 1. The two multiplex outputs are open drain.
MOD = 0. The two multiplex outputs are at low impedance
DCKM
Double clock for Multiplex.
DCKM = 1. DCL is twice data rate (Ex : if Data Rate = 2048 kb/s,DCL = 4096 kHz).
DCKM = 0. DCL is simple clock.
PCM CONFIGURATION REGISTER (PCONF)
7
0
0
TSNB
DEL
PFSP
ODL
ISPP
POD
SCKP
After Reset 00 (H)
TSNB
Time Slot numbering.
TSNB defines the order of TS on the PCM when the data rate is 4 Mb/s or 8 Mb/s
related to the order of TS on the PCM at 2 Mb/s (see table hereafter).
DEL
Delayed Mode for each PCM.
DEL = 1. A delay of one clock pulse is applied to the first bit of the frame of each PCM.
DEL = 0. PFS indicates the first bit of the frame for each PCM (if OFFSET and shift are
zero).
PFSP
PCM Frame Synchronisation Sampling.
PFSP = 0. PFS signal is sampled on the fall edge of PDC signal.
PFSP = 1. PFS signal is sampled on the rise edge of PDC signal.
ODL
Output Delay.
ODL = 0. The bits are shifted out with zero delay.
ODL = 1. The bits are shifted out with a delay of one half bit time.
ISPP
Input Sampling PCM.
ISPP = 0. The input bit is sampled at half bit time.
ISPP = 1. The input bit is sampled at 3/4 bit time.
POD
PCM Open Drain.
POD = 1. The PCM outputs are open drain
POD = 0. The PCM outputs are at low impedance.
SCKP
Simple clock for PCM.
SCKP = 0. PDC signal is twice data rate. (Ex : if data rate = 2048 kb/s, PDC = 4096
kHz).
SCKP = 1. PDC is simple clock
STLC5460
14/54


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEETDE.COM
War ALLDATASHEET hilfreich?  [ DONATE ]  

Über ALLDATASHEET   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Lesezeichen hinzufügen   |   Linktausch   |   Hersteller
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn