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74LVX74 Datenblatt(Datasheet) 4 Page - STMicroelectronics

Teile-Nr. 74LVX74
Beschreibung  LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS)
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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74LVX74
4/13
Table 7: Dynamic Switching Characteristics
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
± 0.3V
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
VOLP
Dynamic Low Voltage
Quiet Output (note 1, 2)
3.3
CL = 50 pF
0.3
0.5
V
VOLV
-0.5
-0.3
VIHD
Dynamic High Voltage
Input (note 1, 3)
3.3
2
VILD
Dynamic Low Voltage
Input (note 1, 3)
3.3
0.8
Symbol
Parameter
Test Condition
Value
Unit
VCC
(V)
CL
(pF)
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
tPLH tPHL Propagation Delay Time
CK to Q or Q
2.7
15
7.3
15.0
1.0
18.5
1.0
18.5
ns
2.7
50
9.8
18.5
1.0
22.0
1.0
22.0
3.3(*)
15
5.7
9.7
1.0
11.5
1.0
11.5
3.3(*)
50
8.2
13.2
1.0
15.0
1.0
15.0
tPLH tPHL Propagation Delay Time
PR or CLR to Q or Q
2.7
15
8.4
15.6
1.0
18.5
1.0
18.5
ns
2.7
50
10.9
19.1
1.0
22.0
1.0
22.0
3.3(*)
15
6.6
10.1
1.0
12.0
1.0
12.0
3.3(*)
50
9.1
13.6
1.0
15.5
1.0
15.5
tw
Minimum Pulse Width
HIGH or LOW, CK
2.7
50
8.5
10.0
10.0
ns
3.3(*)
50
6.0
7.0
7.0
tw(L)
Minimum Pulse Width
LOW PR or CLR
2.7
50
8.5
10.0
10.0
ns
3.3(*)
50
6.0
7.0
7.0
ts
Minimum Setup Time D
to CK HIGH or LOW
2.7
50
8.0
9.5
9.5
ns
3.3(*)
50
5.5
6.5
6.5
th
Minimum Hold Time D
to CK HIGH or LOW
2.7
50
0.5
0.5
0.5
ns
3.3(*)
50
0.5
0.5
0.5
tREM
Minimum Removal Time
PR or CLR to CK
2.7
50
6.5
7.5
7.5
ns
3.3(*)
50
5.0
5.0
5.0
fMAX
Maximum Clock
Frequency
2.7
15
55
135
50
50
MHz
2.7
50
45
604040
3.3(*)
15
95
145
80
80
3.3(*)
50
60
85
50
50
tOSLH
tOSHL
Output To Output Skew
Time (note1, 2)
2.7
50
0.5
1.0
1.5
1.5
ns
3.3(*)
50
0.5
1.0
1.5
1.5




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