74LVX174MTR datasheet(1/12 Pages) STMICROELECTRONICS

Teilenummer	74LVX174MTR

Bauteilbeschribung	LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR WITH 5V TOLERANT INPUTS

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August 2004

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HIGH SPEED:

fMAX = 180MHz (TYP.) at VCC = 3.3V

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5V TOLERANT INPUTS

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INPUT VOLTAGE LEVEL:

VIL=0.8V, VIH=2V at VCC=3V

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LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

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LOW NOISE:

VOLP = 0.3V (TYP.) at VCC = 3.3V

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

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BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

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OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 174

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IMPROVED LATCH-UP IMMUNITY

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POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX174 is a low voltage CMOS HEX

D-TYPE

FLIP

FLOP

WITH

CLEAR

NON

INVERTING fabricated with sub-micron silicon

gate and double-layer metal wiring C2MOS

technology. It is ideal for low power, battery

operated and low noise 3.3V applications.

Information signals applied to D inputs are

transferred to the Q outputs on the positive going

edge of the clock pulse.

When the CLEAR input is held low, the Q outputs

are held low independently of the other inputs.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LVX174

LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR

WITH 5V TOLERANT INPUTS

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LVX174MTR

TSSOP

74LVX174TTR

TSSOP

SOP

Rev. 3

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Ähnliche Beschreibung - 74LVX174MTR

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