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TDA7502013TR Datenblatt(PDF) 11 Page - STMicroelectronics |
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TDA7502013TR Datenblatt(HTML) 11 Page - STMicroelectronics |
11 / 25 page TDA7502 SAI interface 11/25 3 SAI interface Figure 4. SAI timings Note: TDSP = dsp master clock cycle time = 1/FDSP Figure 5. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 Table 11. Cycles Timing Description Value Unit tsckr Minimum Clock Cycle 4TDSP ns tdt SCKR active edge to data out valid 10 ns tlrs LRCK setup time 5 ns tlrh LRCK hold time 5 ns tsdid SDI setup time 15 ns tsdih SDI hold time 15 ns tsckph Minimum SCK high time 0.35 tsckr ns tsckpl Minimum SCK low time 0.35 tsckr ns VALID SDI0-3 VALID tsckph tsckpl tlrh tlrs tdt LRCKR SCKR (RCKP=0) tsdih tsckr tsdis D02AU1357 LEFT LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) LRCKR (#23) SCKR (#24) SDI0,1,2 (#20, #21, #22) RIGHT D02AU1358 |
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