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LAXP2-8E-5TN114E Datenblatt(PDF) 6 Page - Lattice Semiconductor

Teilenummer LAXP2-8E-5TN114E
Bauteilbeschribung  LA-LatticeXP2 Family Data Sheet
Download  83 Pages
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Hersteller  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

LAXP2-8E-5TN114E Datenblatt(HTML) 6 Page - Lattice Semiconductor

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2-3
Architecture
Lattice Semiconductor
LA-LatticeXP2 Family Data Sheet
Figure 2-2. PFU Diagram
Slice
Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3
contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory,
a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks
along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be com-
bined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset func-
tions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.
Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as posi-
tive/negative edge triggered or level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adja-
cent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has
13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice
2.
Slice
PFU BLock
PFF Block
Resources
Modes
Resources
Modes
Slice 0
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 1
2 LUT4s and 2 Registers
Logic, Ripple, ROM
2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 2
2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers
Logic, Ripple, ROM
Slice 3
2 LUT4s
Logic, ROM
2 LUT4s
Logic, ROM
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
D
D
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
From
Routing
To
Routing
Slice 3
LUT4
LUT4
D
D
D
D
FF
FF
FF
FF
FF
FF


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