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LFSCM3GA80KLUTSEP1F256C Datenblatt(PDF) 8 Page - Lattice Semiconductor |
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LFSCM3GA80KLUTSEP1F256C Datenblatt(HTML) 8 Page - Lattice Semiconductor |
8 / 237 page 2-4 Architecture Lattice Semiconductor LatticeSC/M Family Data Sheet Figure 2-3. Slice Diagram Table 2-1. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FCI Fast Carry In 1 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register Outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT8 2 MUX depending on the slice Output Inter-PFU signal FCO For the right most PFU the fast carry chain output 2 1. See Figure 2-2 for connection details. 2. Requires two PFUs. LUT4 & CARRY LUT4 & CARRY Slice A0 B0 C0 D0 FF/ Latch OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO F CE CLK LSR FF/ Latch OFX1 F1 Q1 F D D M1 FCO from Slice/PFU, FCI into Different Slice/PFU FCI into Slice/PFU, FCO from Different Slice/PFU LUT Expansion Mux M0 OFX0 From Routing To Routing Control Signals selected and inverted per slice in routing Note: some interslice signals not shown. |
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