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LFE250E-6F256I Datenblatt(PDF) 10 Page - Lattice Semiconductor |
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LFE250E-6F256I Datenblatt(HTML) 10 Page - Lattice Semiconductor |
10 / 386 page 2-7 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 2-5. General Purpose PLL (GPLL) Diagram Standard PLL (SPLL) Some of the larger devices have two to six Standard PLLs (SPLLs). SPLLs have the same features as GPLLs but without delay adjustment capability. SPLLs also provide different parametric specifications. For more information, please see the list of additional technical documentation at the end of this data sheet. Table 2-4 provides a description of the signals in the GPLL and SPLL blocks. Table 2-4. GPLL and SPLL Blocks Signal Descriptions Signal I/O Description CLKI I Clock input from external pin or routing CLKFB I PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock (PIN or logic) RST I “1” to reset PLL counters, VCO, charge pumps and M-dividers RSTK I “1” to reset K-divider CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed) CLKOP O PLL output clock to clock tree (no phase shift) CLKOK O PLL output to clock tree through secondary clock divider LOCK O “1” indicates PLL LOCK to CLKI DDAMODE 1 I Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static) DDAIZR 1 I Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on DDAILAG 1 I Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag DDAIDEL[2:0] 1 I Dynamic Delay Input DPA MODES I DPA (Dynamic Phase Adjust/Duty Cycle Select) mode DPHASE [3:0] I DPA Phase Adjust inputs DDDUTY [3:0] — DPA Duty Cycle Select inputs 1. These signals are not available in SPLL. Input Clock Divider (CLKI) Feedback Divider (CLKFB) Delay Adjust Voltage Controlled Oscillator Post Scalar Divider (CLKOP) Phase/Duty Select Secondary Divider (CLKOK) CLKOS CLKOK CLKOP LOCK CLKFB CLKI RST Dynamic Delay Adjustment (from routing or external pin) from CLKOP (PLL internal), from clock net(CLKOP) or from a user clock (pin or logic) Dynamic Adjustment PLLCAP External Pin (Optional External Capacitor) RSTK |
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