AD7625

Preliminary Technical Data

Rev. PrB | Page 6 of 11

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

VDD1

2

VDD2

3

CAP1

4

REFIN

5

EN0

6

EN1

7

VDD2

8

CNV-

24 GND

23 IN+

22 IN-

21 REF/2

20 VDD1

19 VDD1

18 VDD2

17 CLK+

TOP VIEW

Figure 2.

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD1

P

Analog 5V Supply.

Decouple with 10uF and 100nF capacitors.

2

VDD2

P

Analog 2.5V Supply.

The system 2.5V supply should supply this pin first, decoupled with 10uF and 100nF capacitors, then

starred off to other VDD2 pins.

3

CAP1

AO

Connect to a 10nF capacitor.

4

REFIN

AI/O

Pre-Buffer Reference Voltage.

When using the internal reference, this pin outputs the band-gap voltage and is nominally at 1.2V. It can

In either mode, a 10uF capacitor is required. If using an external 4.096V reference (connected to REF), this

pin is a no connect and does not require any capacitor.

5, 6

EN0, EN1

DI

Enable Pins.

EN1

EN0

Operation

0

0

Power down all; ADC, internal reference and reference buffer.

0

1

Enable internal buffer, disable internal reference. An external 1.2V reference

connected to REFIN pin is required.

1

0

Disable internal reference and buffer. An external reference connected to the REF

pin is required.

1

1

Enable all; ADC, internal reference and reference buffer.

7

VDD2

P

Digital 2.5V supply.

8, 9

CNV-, CNV+

DI

Convert Input.

This input has multiple functions. On its rising edge, it samples the analog inputs and initiates a

conversion cycle. CNV+ works as a CMOS input when CNV- is grounded otherwise CNV+, CNV- are LVDS

inputs.

10, 11

D-, D+

D0

LVDS Data Outputs.

The conversion data is output serially on these pins.

12

VIO

P

Input/Output Interface Supply. Nominally 2.5V.

13

GND

P

Ground.

14, 15

DCO-, DCO+

DI/O

LVDS Buffered Clock Outputs.

When DCO+ is grounded, the self-clock interface mode is selected. In this mode, the 16 bit results on D

is preceded by a three bit header (010) to allow synchronization of the data by the digital host with

simple logic.

When DCO+ is not grounded, the echoed clock interface mode is selected. In this mode, DCO± is a copy

of CLK±. The data bits are output on the falling edge of DCO+ and can be latched in the digital host on

the next rising edge of DCO+.

16, 17

CLK-, CLK+

DI

LVDS Clock Inputs.

This clock shifts out the conversion results on the negative edge of CLK+.