FAN2108 datasheet(11/14 Pages) FAIRCHILD

Teilenummer	FAN2108

Bauteilbeschribung	TinyBuck??3-24V Input, 8A, High-Efficiency, Integrated Synchronous Buck Regulator

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Hersteller	FAIRCHILD [Fairchild Semiconductor]

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FAN2108 • Rev. 1.0.0

11

Calculating the Inductor Value

Typically the inductor is set for a ripple current (

ΔIL) of

10% to 35% of the maximum DC load. Regulators

requiring fast transient response use a value on the

high side of this range; while regulators that require very

low output ripple and/or use high-ESR capacitors

restrict allowable ripple current.

f

)

V

-

(1

V

OUT

•

Δ

•

=

L

IN

I

V

L

(4)

where f is the oscillator frequency.

Setting the Ramp Resistor Value

The internal ramp voltage excursion (ΔVRAMP) during tON

should be set to 0.6V at nominal operating point. RRAMP

is approximately:

2

10

18

)

8

.

1

(

6

)

(

−

•

−

=

−

Ω

f

V

x

V

R

IN

OUT

IN

K

RAMP

(5)

where frequency (f) is expressed in KHz.

Setting the Current Limit

There are two levels of current-limit thresholds in

FAN2108. The first level of protection is through an

internal default limit set at the factory to limit output

current beyond normal usage levels. The second level

of protection is externally settable at the ILIM pin.

Current-limit protection is enabled whenever the lower

of the two thresholds is reached. FAN2108 uses its

internal low-side MOSFET for current-sensing. The

current-limit threshold voltage (VILIM) is compared to a

scaled version of voltage drop across the low-side

MOSFET, sampled at the end of each PWM off-

time/cycle. The internal default threshold (with ILIM open)

is temperature compensated.

The ILIM pin can source a 10µA current that can be

used to establish a lower, temperature–dependent,

current-limit threshold by connecting a resistor (RILIM)

between ILIM and AGND. RILIM can be approximated

with the equation:

sw

ramp

out

T

out

K

ILIM

f

R

V

K

I

R

•

+

•

+

=

Ω

6

)

(

10

33

.

3

1

3

95

(6)

where:

I

= Desired current limit setpoint in Amps;

KT

= Normalized temperature coefficient of the

low-side MOSFET (Q2 from Figure 8);

K1

= Overload co-efficient (use 1.2 to 1.4);

VOUT = Set output voltage;

Rramp = Ramp resistor used in KΩ; and

fsw

= Selected switching frequency in KHz.

After 16 consecutive, pulse-by-pulse, current-limit

cycles, the fault latch is set and the regulator shuts

down. Cycling VCC or EN restores operation after a

normal soft-start cycle (refer to Auto-Restart section).

The over-current protection fault latch is active during

the soft-start cycle. Use a 1% resistor for RILIM.

In case RILIM is not connected, the IC uses an internal

default current-limit threshold.

Loop Compensation

The loop is compensated using a feedback network

around the error amplifier. Figure 22 shows a complete

type-3

compensation

network.

For

type-2

compensation, eliminate R3 and C3.

Figure 22. Compensation Network

Since the FAN2108 employs summing current-mode

architecture, type-2 compensation can be used for

many applications. For applications that require wide

loop bandwidth and/or use very low-ESR output

capacitors, type-3 compensation may be required.

Protection

The converter output is monitored and protected

against extreme overload, short-circuit, over-voltage,

under-voltage, and over-temperature conditions.

An internal fault latch is set for any fault intended to

shut down the IC. When the fault latch is set, the IC

discharges VOUT by enhancing the low-side MOSFET

until FB<0.25V. The MOSFET is not turned on again

unless FB>0.5V. This behavior discharges the output

without causing undershoot (negative output voltage).

Under-Voltage Shutdown

If voltage on the FB pin remains below the under-

voltage threshold for 16 consecutive clock cycles, the

fault latch is set and the converter shuts down. This

protection is not active until the internal SS ramp

reaches 1.0V during soft-start.

Over-Voltage Protection / Shutdown

If voltage on the FB pin exceeds the over-voltage

threshold for two consecutive clock cycles, the fault

latch is set and shutdown occurs.

A shorted high-side MOSFET condition is detected

when SW voltage exceeds ~0.7V while the low-side

MOSFET is fully enhanced. The fault latch is set

immediately upon detection.

The two fault protection circuits above are active all the

time, including during soft-start.

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