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FAN5182QSCX_NA3E229 Datenblatt(PDF) 10 Page - Fairchild Semiconductor

Teilenummer FAN5182QSCX_NA3E229
Bauteilbeschribung  Adjustable Output, 1-, 2-, or 3-Phase Synchronous Buck Controller
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Hersteller  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN5182QSCX_NA3E229 Datenblatt(HTML) 10 Page - Fairchild Semiconductor

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© 2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5182 • Rev. 1.1.3
10
Current Control Loop and Thermal
Balance
The FAN5182 adopts low-side MOSFET RDSON sensing
for phase-current balance. The sensed individual phase
current is combined with a fixed internal ramp, then
compared with the common voltage error amplifier
output to balance phase current. This current-balance
information is independent of the average output
current information used for the current limit.
The magnitude of the internal ramp can be set to
optimize transient response of the system. It also tracks
the supply voltage for better line regulation and
transient response. A resistor connected from the
power supply input to the RAMPADJ pin determines the
slope of the internal PWM ramp. Resistors RSW1
through RSW3 (see Figure 7) can be used to adjust
phase current balance. Putting placeholders for these
resistors during the initial PCB layout allows phase-
current balance fine adjustments on the bench if
necessary.
To increase the current in any given phase, increase
RSW for that phase (make RSW = 0Ω for the hottest
phase as the starting point). Increasing RSW to 500Ω
could typically make a substantial increase in this
particular phase current. Increase each RSW value by
small amounts to optimize phase-current balance,
starting with the coolest phase.
Voltage Control Loop
A high gain bandwidth voltage error amplifier is used for
the voltage control loop. The non-inverting input of the
error amplifier is derived from the internal 800mV
reference. The output of the error amplifier, the COMP
pin sets the termination voltage for the internal PWM
ramps plus sensed phase current.
The inverting input (FB) is tied to the center point of a
resistor divider from the output voltage sense point.
Closed-loop compensation is realized via compensator
networks connecting to the FB and COMP pins.
Soft-Start
The soft-start rise time of the output voltage is set by a
parallel capacitor and resistor between the DELAY pin
and ground. The resistor capacitor (RC) time constant
also determines the current-limit latch-off delay time, as
explained in the following section. In UVLO or when EN
is logic low, the DELAY pin is held to ground. After the
UVLO threshold is reached and EN is in logic high
state, the delay capacitor is charged with an internal
20µA current source. The output voltage follows the
ramping voltage on the DELAY pin to limit the inrush
current. The soft-start time depends on the value of
CDLY with a secondary effect from RDLY.
If either EN is logic low or VCC drops below UVLO, the
delay capacitor resets to ground and is ready for
another soft-start cycle.
Figure 8 shows typical start-up waveforms for a soft-
start sequence.
Figure 8. Typical Start-Up Waveforms
Current-Limit and Latch-off Protection
The FAN5182 compares a programmable current-limit
set point to the voltage from the output of the current-
sense amplifier. The level of current limit is set with the
resistor from the ILIMIT pin to ground. During normal
operation, the voltage on ILIMIT is 3V. The current
through the external resistor is internally scaled to give
a current-limit threshold of 10.4mV/µA. If the difference
in voltage between CSREF and CSCOMP rises above
the current-limit threshold, the internal current-limit
amplifier controls the COMP voltage to maintain the
power supply output current at the over-current level.
After the limit is reached, the 3V pull-up voltage source
on the DELAY pin is disconnected and the external
delay capacitor discharges through the external
resistor. A comparator monitors the DELAY pin voltage
and shuts off the controller when the voltage drops
below 1.8V. The current-limit latch-off delay time is
therefore set by the RC time constant discharging the
delay voltage from 3V to 1.8V. Typical over-current
latch-off waveforms are shown in Figure 9.
The controller continues to switch all phases during the
latch-off delay. If the over-current condition is removed
before the 1.8V delay threshold is reached, the controller
resumes normal operation. The over-current recovery
characteristic also depends on the state of PWRGD. If
the output voltage is within the PWRGD window during
over current, the controller resumes normal operation
once the over-current condition is removed. If over-
current causes the output voltage to drop below the
PWRGD threshold, a soft-start cycle is initiated.
Figure 9. Over-Current Latch-Off Waveforms


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