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TDA7521 Datenblatt(PDF) 2 Page - STMicroelectronics |
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TDA7521 Datenblatt(HTML) 2 Page - STMicroelectronics |
2 / 11 page TDA7521 2/11 Figure 1. TDA7521 Block Diagram 1.0 HARDWARE DESCRIPTION 1.1 Clock source and generation The master clock to operate the device is 768 ×Fs (High Frequency mode, HFM) or 384×Fs (Low Frequen- cy mode, LFM). Fs=44.1KHz for CD applications. In either case, the clock is generated by TDA7522: an internal low-jitter Charge-Pump PLL (CPPLL) and a Finite State Machine (FSM) synthesize all the needed clocks for the internal blocks: a 512 ×Fs for the DAC and three 384×Fs (HFM) or 192×Fs (LFM), with dif- ferent phases for ADCs and output digital multiplexer. The required loop filter network is made up of a 160pF capacitor from FILT to GND_pll in parallel with the series of a 10nF and a 4K Ω resistor. All clock- related setups are communicated to TDA7521 via UART interface. 1.2 Voltage references REFIN is an internal voltage reference generated by a resistor divider between VCC_dac and VSS_dac. Nominal value (with VCC_dac=5V) is REFIN=2.5V. Careful filtering of this pin is essential; recommended value of external capacitor is 47 µF paralleled with 100nF ceramic. REFOUT is a 2.5V (nominal) buffered output to bias the pickup. All the internal voltage references for ADCs and DACs are generated by band- gap-based circuits, thus allowing to reduce the noise induced by the power supply. AC BD E F SDA SCL LD MD DL DR OUTL OUTR Control I/F Laser Driver Stereo DAC RF ADC Servo ADC RF ADC I/V I/V I/V I/V Output MUX d0 d1 d2 d3 d4 d5 d6/OF d7/UF SYNC HF MON REF Gen REF IN REF OUT PON REXT CLOCK Mgr CKIN FILT MUTEL MUTER |
Ähnliche Teilenummer - TDA7521 |
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Ähnliche Beschreibung - TDA7521 |
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