Datenblatt-Suchmaschine für elektronische Bauteile |
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AD1989BJCPZ Datenblatt(PDF) 11 Page - Analog Devices |
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AD1989BJCPZ Datenblatt(HTML) 11 Page - Analog Devices |
11 / 20 page AD1989B Rev. 0 | Page 11 of 20 | August 2008 POWER AND GROUND DVGPIO 3.3 V ± 10% 3 I GPIO and S/PDIF Out (1 and 2) Signal Level (independent of DVIO). Connect to 3.3 V ±10%. DVIO 3.3 V ± 10% or DVIO 1.5 V ± 5.5% 4 I Connect to the I/O voltage used for the HD Audio controller signals. DVSS 7 I Digital Supply Return (Ground). DVDD 3.3 V ± 10% 9 I Digital Supply Voltage 3.3 V. This is regulated down to Pin 1 to supply the internal digital core. AVDD 3.3 V ± 5% 25, 38 I CAUTION: DO NOT APPLY 5.0 V TO THESE PINS! Analog Supply Voltage 3.3 V ONLY. Note: AVDD supplies should be well regulated and filtered as supply noise degrades audio performance. MIC_BIAS_IN 33 I Source for Microphone Bias Circuitry. Connect this pin to 5.0 V via a low-pass filter. When connected this way the AD1989B is capable of providing +3.95 V as a mic bias to all of the MIC_BIAS pins. If 5 V is not available, connect this pin to +3.3 V (AVDD) via a low-pass filter. The AD1989B produces a mic bias voltage relative to the AVDD supply (typically 3.0 V @ AVDD = 3.3 V). AVSS 26, 42 I Analog Supply Return (Ground). AVSS should be connected to DVSS using a conductive trace under, or close to, the AD1989B. Table 4. Pin Function Descriptions (Continued) Mnemonic Pin No. Function Description The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function). |
Ähnliche Teilenummer - AD1989BJCPZ |
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Ähnliche Beschreibung - AD1989BJCPZ |
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