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CDB42325 Datenblatt(PDF) 5 Page - Cirrus Logic

Teilenummer CDB42325
Bauteilbeschribung  10-In, 6-Out, 2 Vrms Audio CODEC with Headphone
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CDB42325 Datenblatt(HTML) 5 Page - Cirrus Logic

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DS838A2
5
CS42325
6.8.1 DAC2 MCLK Source ............................................................................................................. 52
6.8.2 DAC2 Serial Port Source ....................................................................................................... 52
6.8.3 DAC2 Digital Interface Format (DAC2_DIF) .......................................................................... 52
6.9 ADC Control (Address 0Ah) ........................................................................................................... 52
6.9.1 ADC High-Pass Filter Freeze ................................................................................................ 52
6.9.2 ADC Soft Ramp Control ........................................................................................................ 52
6.9.3 Analog Input Selection .......................................................................................................... 53
6.10 DAC1 Control (Address 0Bh) ....................................................................................................... 53
6.10.1 DAC1 De-Emphasis Control ................................................................................................53
6.10.2 DAC1 Single Volume Control ..............................................................................................53
6.10.3 DAC1 Soft Ramp Control .................................................................................................... 53
6.10.4 DAC1 Zero Cross Control ................................................................................................... 54
6.10.5 DAC1 Loop-Back ................................................................................................................. 54
6.10.6 DAC1 Invert Signal Polarity ................................................................................................. 54
6.10.7 DAC1 Channel Mixer ........................................................................................................... 54
6.11 DAC2 Control (Address 0Ch) ....................................................................................................... 55
6.11.1 DAC2 De-Emphasis Control ................................................................................................55
6.11.2 DAC2 Single Volume Control ..............................................................................................55
6.11.3 DAC2 Soft Ramp Control .................................................................................................... 55
6.11.4 DAC2 Zero Cross Control ................................................................................................... 55
6.11.5 DAC2 Loop-Back ................................................................................................................. 56
6.11.6 DAC2 Invert Signal Polarity ................................................................................................. 56
6.11.7 DAC2 Channel Mixer ........................................................................................................... 56
6.12 AOUT1 Control (Address 0Dh) ..................................................................................................... 56
6.12.1 External Mute Control Pin ................................................................................................... 56
6.12.2 AOUT1 Select ..................................................................................................................... 56
6.13 AOUT2 Control (Address 0Eh) ..................................................................................................... 57
6.13.1 External Mute Control Pin ................................................................................................... 57
6.13.2 AOUT2 Select ..................................................................................................................... 57
6.14 AOUT3/HP Control (Address 0Fh) ............................................................................................... 57
6.14.1 External Mute Control Pin ................................................................................................... 57
6.14.2 AOUT3/HP Select ............................................................................................................... 58
6.15 ADCx Volume Control: ADCA (Address 10h) & ADCB (Address 11h) ......................................... 58
6.16 DAC1x Volume Control: DAC1A (Address 12h) & DAC1B (Address 13h) ................................... 58
6.17 DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h) ................................... 59
6.18 Interrupt Mode (Address 16h) ....................................................................................................... 59
6.19 Interrupt Mask (Address 17h) ....................................................................................................... 59
6.19.1 DAC2 Auto Mute Left Mask (DAC2_AMUTELM) ................................................................ 60
6.19.2 DAC2 Auto Mute Right Mask (DAC2_AMUTERM) ............................................................. 60
6.19.3 DAC1 Auto Mute Left Mask (DAC1_AMUTELM) ................................................................ 60
6.19.4 DAC1 Auto Mute Right Mask (DAC1_AMUTELM) .............................................................. 60
6.19.5 Serial Port 2 Clock Error Mask (SP2_CLKERRM) .............................................................. 60
6.19.6 Serial Port 1 Clock Error Mask (SP1_CLKERRM) .............................................................. 60
6.19.7 ADC Positive Overflow Mask (ADC_OVFLPM) ................................................................... 61
6.19.8 ADC Negative Overflow Mask (ADC_OVFLNM) ................................................................. 61
6.20 Interrupt Status (Address 18h) (Read Only) ................................................................................. 61
6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL) ................................................... 61
6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER) ................................................ 61
6.20.3 DAC1 Auto Mute Left Interrupt Status (DAC1_AMUTEL) ................................................... 62
6.20.4 DAC1 Auto Mute Right Interrupt Status (DAC1_AMUTEL) ................................................. 62
6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR) ................................................. 62
6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR) ................................................. 62
6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP) ............................................................ 62
6.20.8 ADC Negative Overflow Interrupt Bit (ADC_OVFLN) .......................................................... 63


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