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ML2726 Datenblatt(PDF) 10 Page - SIRENZA MICRODEVICES

Teilenummer ML2726
Bauteilbeschribung  2.4GHz Low-IF 2.0Mbps FSK Transceiver
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ML2726
PRELIMINARY DATASHEET
OCT 2007
EDS-105982 REV P01
10
MODE CONTROL AND INTERFACE LINES
1
XCEN
I (CMOS)
Enables the bandgap reference and
voltage regulators when high. Consumes
only leakage current in STANDBY mode
when low. This is a CMOS input, and the
thresholds are referenced to VDD and
VSS.
2
RXON
I (CMOS)
TX/RX Control Input. Switches the
transceiver between TRANSMIT and
RECEIVE modes. Circuits are powered
up and signal paths reconfigured
according to the operating mode. This is
a CMOS input, and the thresholds are
referenced to VDD and VSS.
1
VSS
XCEN
VDD
RXON
DIN
2
30
31
8
3
PAON
O (CMOS)
PA Control Output. Enables the off-chip
PA at the correct times in a Transmit slot.
Goes high when transmit RF is present
at TXO; goes low
5μs before transmit RF
is removed from TXO. Has interlock logic
to shut down the PA if the PLL does not
lock.
31
VSS
VDD
3
PAON
8
9
FREF
I
Input for the 9.216MHz, 12.288MHz,
18.432MHz or 25.576MHz reference
frequency. This input is used as the
reference frequency for the PLL and as a
calibration frequency for the on-chip
filters. An AC-coupled sine or square
wave source drives this self-biased input.
9
VSS
FREF
VCCA
24
8
40k
40k
11
QPO
O
Charge Pump Output of the phase
detector. This is connected to the
external PLL loop filter.
10
VSS
RVPLL
11 QPO
8


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