Datenblatt-Suchmaschine für elektronische Bauteile |
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TSC21020F-20MC-E Datenblatt(PDF) 11 Page - ATMEL Corporation |
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TSC21020F-20MC-E Datenblatt(HTML) 11 Page - ATMEL Corporation |
11 / 50 page 11 TSC21020F 4153H–AERO–04/07 Pin Descriptions This section describes the pins of the TSC21020F. When groups of pins are identified with subscripts, e.g. PMD47-0, the highest numbered pin is the MSB (in this case, PMD47). Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST). Those that are asynchronous (A) can be asserted asynchronously to CLKIN. Note: O = Output; I = Input; S = Synchronous; A = Asynchronous; P = Power Supply; G = Ground. Pin Name Type Function PMA 23-0 O Program Memory Address. The TSC21020F outputs an address in program memory on these pins. PMD47-0 I/O Program Memory Data. The TSC21020F inputs and outputs data and instructions on these pins. 32-bit fixed-point data and 32-bit single- precision floating-point data is transferred over bits 47-16 of the PMD bus. PMS 1-0 O Program Memory Select lines. These pins are asserted as chip selects for the corresponding banks of program memory. Memory banks must be defined in the memory control registers. These pins are decoded program memory address lines and provide an early indication of a possible bus cycle. PMRD O Program Memory Read strobe. This pin is asserted when the TSC21020F reads from program memory. PMWR O Program Memory Write strobe. This pin is asserted when the TSC21020F writes to program memory. PMACK I/S Program Memory Acknowledge. An external device de-asserts this input to add wait states to a memory access. PMPAGE O Program Memory Page Boundary. The TSC21020F asserts this pin to signal that a program memory page boundary has been crossed. Memory pages must be defined in the memory control registers. PMTS I/S Program Memory Three-State Control. PMTS places the program memory address, data, selects, and strobes in a high-impedance state. If PMTS is asserted while a PM access is occurring, the processor will halt and the memory access will not be completed. PMACK must be asserted for at least one cycle when PMTS is de-asserted to allow any pending memory access to complete properly. PMTS should only be asserted (low) during an active memory access cycle. DMA 31-0 O Data Memory Address. The TSC21020F outputs an address in data memory on these pins. DMD 39-0 I/O Data Memory Data. The TSC21020F inputs and outputs data on these pins. 32-bit fixed-point data and 32-bit single-precision floating-point data is transferred over bits 39-8 of the DMD bus. DMS3-0 O Data Memory Select lines. These pins are asserted as chip selects for the corresponding banks of data memory. Memory banks must be defined in the memory control registers. These pins are decoded data memory address lines and provide an early indication of a possible bus cycle. |
Ähnliche Teilenummer - TSC21020F-20MC-E |
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Ähnliche Beschreibung - TSC21020F-20MC-E |
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