MC54/74HC589

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

3–8

PARALLEL

DATA

INPUTS

10

14

11

13

12

15

1

2

3

4

5

6

7

OUTPUT ENABLE

SA

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

LATCH CLOCK

A

B

C

D

E

F

G

H

STAGE A

STAGE B

STAGE C*

STAGE D*

STAGE E*

STAGE F*

STAGE G*

STAGE H

VCC

9

QH

D

C

Q

D

C

Q

D

C

Q

S

R

D

C

Q

S

R

D

C

Q

D

C

Q

S

R

*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

LOGIC DETAIL