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STC5230-I Datenblatt(PDF) 3 Page - Connor-Winfield Corporation |
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STC5230-I Datenblatt(HTML) 3 Page - Connor-Winfield Corporation |
3 / 48 page Data Sheet #: TM102 Page 3 of 48 Rev: P01 Date: August 22, 2007 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5230 Synchronous Clock for SETS Data Sheet Preliminary Table of Figures Figure 1: Functional Block Diagram ................................................................................................................. 1 Figure 2: Operating mode transition in automatic reference selection (Master mode)................................... 14 Figure 3: Activity Monitor ................................................................................................................................ 15 Figure 4: Reference Qualification Scheme..................................................................................................... 16 Figure 5: Output Clocks.................................................................................................................................. 17 Figure 6: T0 clock output Phase Alignment.................................................................................................... 17 Figure 7: Master/Slave Pair ............................................................................................................................ 18 Figure 8: T0 CLK0-6,8 Phase Alignment and Master/Slave skew Control ..................................................... 18 Figure 9: T4 CLK7 Master/Slave Skew Control.............................................................................................. 19 Figure 10: EEPROM Configuration ................................................................................................................ 20 Figure 11: Serial Bus Timing, Read access ................................................................................................... 22 Figure 12: Serial Bus Timing, Write access.................................................................................................... 22 Figure 13: Noise Transfer Functions .............................................................................................................. 43 Figure 14: Powers and Grounds .................................................................................................................... 44 |
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