TC7109ACPL datasheet(11/21 Pages) TELCOM

Teilenummer	TC7109ACPL

Bauteilbeschribung	12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

Download	21 Pages

Scroll/Zoom	100%

Hersteller	TELCOM [TelCom Semiconductor, Inc]

Direct Link	http://www.telcom-semi.com

Logo

11 / 21 page

3-101

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

Handshake Mode

An alternative means of interfacing the TC7109A to

digital systems is provided when the handshake output

mode of the TC7109A becomes active in controlling the

flow of data instead of passively responding to chip and

byte enable inputs. This mode allows a direct interface

between the TC7109A and industry-standard UARTs with

no external logic required. The TC7109A provides all the

control and flag signals necessary to sequence the two

bytes of data into the UART and initiate their transmission

in serial form when triggered into the handshake mode.

The cost of designing remote data acquisition stations is

reduced using serial data transmission to minimize the

number of lines to the central controlling processor.

The MODE input controls the handshake mode. When

the MODE input is held HIGH, the TC7109A enters the

handshake mode after new data has been stored in the

output latches at the end of every conversion performed

(see Figures 7 and 8). Entry into the handshake mode may

be triggered on demand by the MODE input. At any time

during the conversion cycle, the LOW-to-HIGH transition of

a short pulse at the MODE input will cause immediate entry

into the handshake mode. If this pulse occurs while new

data is being stored, the entry into handshake mode is

delayed until the data is stable. The MODE input is ignored

in the handshake mode, and until the converter completes

the output cycle and clears the handshake mode, data

updating will be inhibited (see Figure 9).

When the MODE input is HIGH or when the converter

enters the handshake mode, the chip and byte enable

inputs become TTL-compatible outputs which provide the

output cycle control signals (see Figures 7, 8 and 9).

The SEND input is used by the converter as an indica-

tion of the ability of the receiving device (such as a UART)

to accept data in the handshake mode. The sequence of

the output cycle with SEND held HIGH is shown in Figure

7. The handshake mode (internal MODE HIGH) is entered

after the data latch pulse (the CE/LOAD, LBEN and HBEN

terminals are active as outputs since MODE remains HIGH).

The HIGH level at the SEND input is sensed on the

same HIGH-to-LOW internal clock edge. On the next LOW-

to-HIGH internal clock edge, the high-order byte (bits 9

through 12, POL, and OR) outputs are enabled and the CE/

LOAD and the HBEN outputs assume a LOW level. The

CE/LOAD output remains LOW for one full internal clock

period only; the data outputs remain active for 1-1/2 inter-

nal clock periods; and the high-byte enable remains LOW

for 2 clock periods. The CE/LOAD output LOW level or

LOW-to-HIGH edge may be used as a synchronizing sig-

nal to ensure valid data, and the byte enable as an output

may be used as a byte identification flag. With SEND

remaining HIGH the converter completes the output cycle

using CE/LOAD and LBEN while the low-order byte out-

puts (bits 1 through 8) are activated. When both bytes are

sent, the handshake mode is terminated. The typical UART

interfacing timing is shown in Figure 8. The SEND input is

used to delay portions of the sequence, or handshake, to

ensure correct data transfer. This timing diagram shows an

industry-standard HD6403 or CDP1854 CMOS UART to

interface to serial data channels. The SEND input to the

TC7109A is driven by the TBRE (Transmitter Buffer Regis-

ter Empty) output of the UART, and the CE/LOAD input of

the TC7109A drives the TBRL (Transmitter Buffer Register

Load) input to the UART. The eight transmitter buffer regis-

ter inputs accept the parallel data outputs. With the UART

transmitter buffer register empty, the SEND input will be

HIGH when the handshake mode is entered after new data

is stored. The high-order byte outputs become active and

the CE/LOAD and HBEN inputs will go LOW after SEND is

sensed. When CE/LOAD goes HIGH at the end of one

clock period, the high-order byte data is clocked into the

UART transmitter buffer register. The UART TBRE output

will go LOW, which halts the output cycle with the HBEN

output LOW, and the high-order byte outputs active. When

the UART has transferred the data to the transmitter regis-

ter and cleared the transmitter buffer register, the TBRE

returns HIGH. The high-order byte outputs are disabled on

the next TC7109A internal clock HIGH-to-LOW edge, and

one-half internal clock later, the HBEN output returns HIGH.

The CE/LOAD and LBEN outputs go LOW at the same

time as the low-order byte outputs become active. When

the CE/LOAD returns HIGH at the end of one clock period,

the low-order data is clocked into the UART transmitter

buffer register, and TBRE again goes LOW. The next

TC7109A internal clock HIGH-to-LOW edge will sense

when TBRE returns to a HIGH, disabling the data inputs.

One-half internal clock later, the handshake mode is cleared,

and the CE/LOAD, HBEN

and LBEN terminals return

HIGH and stay active, if MODE still remains HIGH.

Handshake output sequences may be performed on

demand by triggering the converter into handshake mode

with a LOW-to-HIGH edge on the MODE input. A hand-

shake output sequence triggered is shown in Figure 9. The

SEND input is LOW when the converter enters handshake

mode. The whole output sequence is controlled by the

SEND input, and the sequence for the first (high order) byte

is similar to the sequence for the second byte.

Figure 9 also shows that the output sequence can take

longer than a conversion cycle. New data will not be latched

when the handshake mode is still in progress and is there-

fore lost.

TC7109

TC7109A

12-BIT

µP-COMPATIBLE

ANALOG-TO-DIGITAL CONVERTERS

TC7109ACPL Datenblatt(PDF) 11 Page - TelCom Semiconductor, Inc

TC7109ACPL Datenblatt(HTML) 11 Page - TelCom Semiconductor, Inc

Ähnliche Teilenummer - TC7109ACPL

Ähnliche Beschreibung - TC7109ACPL

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Datenblatt Download

Link URL