Datenblatt-Suchmaschine für elektronische Bauteile |
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TC7106IJL Datenblatt(PDF) 6 Page - TelCom Semiconductor, Inc |
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TC7106IJL Datenblatt(HTML) 6 Page - TelCom Semiconductor, Inc |
6 / 19 page 3-188 TELCOM SEMICONDUCTOR, INC. TC7106 TC7106A TC7107 TC7107A 3-1/2 DIGIT A/D CONVERTERS GENERAL THEORY OF OPERATION DUAL SLOPE CONVERSION PRINCIPLES (All Pin Designations Refer to the 40-Pin DIP) The TC7106A and TC7107A are dual slope, integrating analog-to-digital converters. An understanding of the dual slope conversion technique will aid in following the detailed operation theory. The conventional dual slope converter measurement cycle has two distinct phases: • Input Signal Integration • Reference Voltage Integration (Deintegration) The input signal being converted is integrated for a fixed time period (TSI). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (TRI). (Figure 2A). In a simple dual slope converter a complete conversion requires the integrator output to “ramp-up” and “ramp- down.” A simple mathematical equation relates the input signal, reference voltage and integration time: VIN(t)dt = Figure 2A. Basic Dual Slope Converter 1 RC ∫TSI VRTRI RC 0 where: VR = Reference Voltage TSI = Signal Integration Time (Fixed) TRI = Reference Voltage Integration Time (Variable) For a constant VIN: VIN = VR TRI TSI REF VOLTAGE ANALOG INPUT SIGNAL DISPLAY SWITCH DRIVER CONTROL LOGIC CLOCK COUNTER POLARITY CONTROL PHASE CONTROL VIN VIN VFULL SCALE 1/2 VFULL SCALE VARIABLE REFERENCE INTEGRATE TIME FIXED SIGNAL INTEGRATE TIME INTEGRATOR C COMPARATOR ≈ ≈ +/– PIN DESCRIPTION (Cont.) Pin No. Pin No. 40-Pin PDIP 40-Pin PDIP (Normal) (Reverse) Symbol Description 34 (7) C + REF A 0.1 µF capacitor is used in most applications. If a large common- mode voltage exists (for example, the V –IN pin is not at analog common), and a 200mV scale is used, a 1 µF capacitor is recom- mended and will hold the roll-over error to 0.5 count. 35 (6) V– REF See pin 36. 36 (5) V+ REF The analog input required to generate a full-scale output (1999 counts). Place 100mV between pins 35 and 36 for 199.9mV full-scale. Place 1V between pins 35 and 36 for 2V full scale. See paragraph on REFERENCE VOLTAGE. 37 (4) Test Lamp test. When pulled HIGH (to V+) all segments will be turned on and the display should read –1888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under TEST for additional information. 38 (3) OSC3 See pin 40. 39 (2) OSC2 See pin 40. 40 (1) OSC1 Pins 40, 39, 38 make up the oscillator section. For a 48kHz clock (3 readings per section), connect pin 40 to the junction of a 100k Ω resistor and a 100pF capacitor. The 100k Ω resistor is tied to pin 39 and the 100pF capacitor is tied to pin 38. |
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