UAA145

TELEFUNKEN Semiconductors

Rev. A1, 29-May-96

3 (11)

Comparator (Differential Amplifier)

and Memory

In the (voltage) comparator stage, the ramp voltage is

comparator switches whenever the instantaneous ramp

voltage is the same as the shift voltage (corresponding to

the desired phase angle), thereby causing the memory to

be set, i.e. the integrated thyristor in memory is to be

turned on. The time delay between the signal input and

the comparator output signal is proportional to the

required phase angle. Design of the circuit is such that the

memory content is reset only during the instant of zero

crossover, the reset signal always overriding the set

signal. This effectively prevents the generation of

additional output pulses and causes any pulse already

started to be immediately inhibited on application of an

inhibit signal to Pin 6. The memory content can also be

reset via Pin 6. Thus the memory ensures that any noise

(negative voltage transients) superimposed on the shift

signal at Pin 8 cannot give rise to the generation of

multiple pulses during the half-cycle.

Pulse Generator

(Monostable Multivibrator)

The memory setting pulse also triggers a monostable

stage. The duration of the pulse produced by the mono-

Pin 11.

Channel Selection and Output

Amplifier

A pulse is produced at either output Pin 10 or Pin 14 if

derived from the pulse generator are applied to the output

transistors via OR gates controlled by the half-cycle

signals derived from the sync stage. During the positive

so that an output pulse is produced at Pin 14. The same is

valid for Pin 10 during the negative half-cycle.

Pulse Diagram

Figure 3 shows the pulse voltage waveforms measured at

various points of the circuit, all signals being time

referenced to the sync signal shown at the top. The input

circuit limits any signal applied to

"0.8 V at Pin 9. The

sync pulse can be measured at Pin 16, whereas the ramp

waveform and the pulse phasing rear limit (

Pin 7. The time relationship between the shift voltage ap-

plied to Pin 8 and the ramp waveform is indicated by

dotted lines. A pulse trigger signal is produced whenever

the ramp crosses the shift level. The memory control

pulse can be monitored by means of an oscilloscope ap-

the waveforms at Pin 10 and Pin 11 are those of the output

pulses.

Figure 3. Pulse diagram

Influence of External Components,

Syncronization Time

An ideal 0 to 180

_ shift range and perfect half-cycle pulse

timing symmetry are attained, if the sync pulse duration

is kept short. However, there is a lower pulse duration

limit, which is governed by the time required to charge

As can be seen, it takes about 35

for sync pulse of 230 V

∼. The lower the sync voltage,

longer is the sync pulse.

A minimum of 50

ms (max. 200 ms) input sync pulse is

required for a pulse symmetry of

Dö x"3°.