Datenblatt-Suchmaschine für elektronische Bauteile |
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MC-ACT-UL2LINK-NET Datenblatt(PDF) 1 Page - Actel Corporation |
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MC-ACT-UL2LINK-NET Datenblatt(HTML) 1 Page - Actel Corporation |
1 / 7 page TX Master RX Master TX FIFO tex t RX FIFO ing_perr increment a_full wr_clk wr_enb wr_data empty flag decrement rd_enb rd_data egr_data egr_addr egr_soc egr_enb_n egr_clav egr_prty egr_clk ing_data ing_addr ing_soc ing_enb_n ing_clav ing_prty ing_clk wr_data wr_enb a_full increment soc flag decrement rd_data rd_clk rd_enb AvnetCore: Datasheet UTOPIA Level 2 Link Intended Use: — ATM Cell Processors — ATM Switch Fabrics Features: — Function compatible with ATM Forum af-phy-0017.000 & af-phy-0039.000 — Asynchronous/synchronous FIFO using RAM — Up to 31 PHYs supported — 8/16 bit interfaces supported — 52/54 byte cells supported — Simple system side FIFO interface — Simple system side FIFO interface Targeted Devices: — Axcelerator Family Core Deliverables: — Netlist Version > Netlist compatible with the Actel Designer place and route tool > Compiled RTL simulation model, compliant with the Actel Libero® environment — RTL Version > VHDL Source Code — All > User Guide > Test Bench Synthesis and Simulation Support: — Synthesis: Synplicity — Simulation: ModelSim — Other tools supported upon request Verification: — Test Bench — Test Vectors UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 2 defines the interface between the ATM or LINK layer and a Physical Layer (PHY) device. The UTOPIA level 2 standard defines a full duplex interface with a Master/Slave format. The Slave or LINK layer device responds to the requests from the PHY or Master device. The Master performs PHY arbitration and initiates data transfers to and from the Slave. The ATM forum has defined the UTOPIA Level 2 as either 8 or 16 bits in width, at up to 50MHz, supporting an OC12 channel at 622Mbps. Version 1.0, July 2006 Block Diagram |
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