Signal

Width

Direction

Description

dtr_n

num_channels

Output

Data Terminal Ready.

This signal, when driven low, indicates to the data set that the data terminal is powered up. This

signal can be asserted by setting bit 0 of the MCR register.

out1_n

num_channels

Output

Each channel has 2 general-purpose output pins.

data_out[7:0]

num_channels

Output

Each channel has 2 general-purpose output pins.

rst

1

Input

Buffered processed active high reset signal (should come from global buffer output)

earlyRst

1

Input

Buffered processed active high early reset signal (should come from global buffer output)

rst_2_gbuf

1

Output

Processed active high reset signal (should feed input to global buffer)

earlyRst_2_gbuf

1

Output

Processed active high early reset signal (should feed input to global buffer)

Table 1: Top Level Module Signal Descriptions

UARTM

This is the top level of the core. Its main purpose is to serve as a container to instantiate the modules shown in the block diagram.

UART_WRAPPER

The DDR Interface (ddr_interface) module is responsible for maintaining the bi-directional ddr_data bus, and for asserting all address and command signals to the

SDRAM. For a write operation, this module reads from the larger sys_data bus and, using the 2x clock and muxes, constructs the DDR data bus, writing out a new

value on every rising edge of the 2x clock which is strobed into the DDR SDRAM with ddr_dqs. For read operations, the opposite must occur. The Data Path reads in

the DDR data using sys_clk_fb rising edge as the time reference, and de-muxes the data into two separate 1x clock pipelines. These two 1x clock pipelines are then

concatenated to form the larger sys_data bus, which is provided to the user.

Characteristics of this time-sliced UART core with portions of the design which are not time-sliced. To accomplish this interfacing, two modules are provided. A

Parallel to Serial module, named muart_p2s, which receives parallel input (all channels simultaneously) and serializes these terms at the appropriate channel time

slots to the UART core. A Serial to Parallel module, named muart_s2p, which receives the time-sliced output of the UART core, and updates the appropriate channel

state in due time.

UART core

The UART core is a net-list processed standard 8250 UART. This UART consists of 5 blocks, Receive, Transmit, Interrupt, Baud Rate, and Modem which are briefly

described below.

UART_RECV

Receiver. This block filters the serial input data (SIN), detects the start bit, controls the sampling of SIN, determines when a complete character is shifted into the

receive shift register, and stores the received character into the receive FIFO. When the correct number of bytes have been stored in the FIFO as set by bits 6 and

7 of the FIFO control register (FCR), an interrupt is sent to the microprocessor which fetches the byte from the receive holding register (RHR) for the channel that

caused the interrupt. Parity, framing, and overrun errors are detected and their corresponding bits are set in the line status register (LSR). All operations in this block

are synchronous to the system clock CLK and enabled with the receiver clock enable, RX_CE. RX_CE must occur at 16x the expected serial bit rate.

UART_XMIT

Transmitter. This block accepts 8-bit parallel data, stores it onto the FIFO, retrieves it from the FIFO, serializes it, appends start, stop, and parity bits as needed, and

shifts this data out on SOUT. This block generates an interrupt when the external FIFO is empty. All operations in this block are synchronous to CLK and enabled with

the transmitter clock enable, TX_CE, except for writing data to the THR which is synchronous to CLK and enabled with the THR_CE. TX_CE must occur at 16x the

desired serial bit rate.

UART_MODEM

Modem Control and Status Logic. This block provides status of the modem input lines for each channel, both current status and change of state. The modem control

lines are also generated here. An interrupt is generated on the low to high transition of RI_L or any change of state of CTS_L, DCD_L, and DSR_L. All operations in

this block are synchronous to CLK.

UART_INTR

Interrupt Logic. For each channel, this block prioritizes the four interrupt sources and encodes them into a 3-bit Internal version of the Interrupt Status Register value,

ISR[2:0], and sends an internal interrupt request output to the HOST_REGISTERS module which adds FIFO interrupts to the internal version of ISr[2:0]. A 4-bit Inter-

rupt Enable Register input, IER[3:0], allows the user to individually mask each interrupt input. Any active interrupt source that has its corresponding IER bit set, will

cause IRQ to be asserted. In order to clear the interrupt, the action listed in the following table must be performed. In order to determine the exact cause of an inter-

rupt, the microprocessor should read the ISR. If IIR[0] is low, there is a pending interrupt and the source is determined by decoding the Interrupt Status Bits, ISR [2:1].

For a Receiver Line Status Interrupt, the LSR must be read to further determine what type of error or errors have caused the assertion of INTRPT. If LSR[7] is set,

there is either a parity error, framing error, or break indication associated with one of the characters in the Receive FIFO. LSR[4:2] will always reflect the error status

for the character at the top of the FIFO. If the Receive FIFO is empty, LSR[4:2] will be all zeroes.