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74FCT16244TPACTG4 Datenblatt(PDF) 1 Page - Texas Instruments |
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74FCT16244TPACTG4 Datenblatt(HTML) 1 Page - Texas Instruments |
1 / 8 page 16-Bit Buffers/Line Drivers SCCS028 - December 1987 - Revised March 2000 Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16244T CY74FCT162244T CY74FCT162H244T Copyright © 2000, Texas Instruments Incorporated 1CY74FCT16444T/2 H244T Features • FCT-E speed at 3.2 ns • Power-off disable outputs permits live insertion • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of –40˚C to +85˚C • VCC = 5V ± 10% CY74FCT16244T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C CY74FCT162244T Features: • Balanced output drivers: 24 mA • Reduced system switching noise • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25˚C CY74FCT162H244T Features: • Bus hold on data inputs • Eliminates the need for external pull-up or pull-down resistors Functional Description These 16-bit buffers/line drivers are designed for use in memory driver, clock driver, or other bus interface applications, where high-speed and low power are required. With flow-through pinout and small shrink packaging board layout is simplified. The three-state controls are designed to allow 4-bit, 8-bit or combined 16-bit operation. The outputs are de- signed with a power-off disable feature to allow for live insertion of boards. The CY74FCT16244T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162244T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for mini- mal undershoot and reduced ground bounce. The CY74FCT162244T is ideal for driving transmission lines. The CY74FCT162H244T is a 24-mA balanced output part that has “bus hold” on the data inputs. The device retains the in- put’s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and pre- vents floating inputs. GND Logic Block Diagrams CY74FCT16244T, CY74FCT162244T, CY74FCT162H244T Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 33 32 31 30 29 25 26 27 28 36 35 1OE 34 SSOP/TSSOP Top View 1Y1 1Y2 1Y3 1Y4 13 14 15 16 17 18 19 20 21 22 23 24 45 44 43 42 41 37 38 39 40 48 47 46 1A1 1A2 1A3 1A4 1OE 2Y1 2Y2 2Y3 2Y4 2A1 2A2 2A3 2A4 2OE 1Y1 1Y2 1Y3 1Y4 1A1 1A2 1A3 1A4 2OE GND GND VCC 2Y3 2Y4 2Y1 2Y2 2A1 2A2 2A3 2A4 VCC GND GND 3Y3 3Y4 3Y1 3Y2 3A1 3A2 3A3 3A4 GND GND VCC 4Y3 4Y4 4Y1 4Y2 4A1 4A2 4A3 4A4 VCC GND 4OE 3OE 3Y1 3Y2 3Y3 3Y4 3A1 3A2 3A3 3A4 3OE 4Y1 4Y2 4Y3 4Y4 4A1 4A2 4A3 4A4 4OE FCT16244–1 FCT16244–2 FCT16244–3 FCT16244–4 FCT16244–5 16244T 162244T 162H244T |
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