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TDA9951 Datenblatt(PDF) 4 Page - NXP Semiconductors |
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TDA9951 Datenblatt(HTML) 4 Page - NXP Semiconductors |
4 / 41 page TDA9951_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 7 August 2008 4 of 41 NXP Semiconductors TDA9951 CEC/I2C-bus translator 7. Pinning information 7.1 Pinning 7.2 Pin description Fig 2. Pin configuration TDA9951 VFD_CLK IR_DAT VFD_DAT IR_VAL SBY A0 INT RSVD2 CEC_OUT KROW0 RST_N KROW1 VSS KROW2 XTAL1 VDD XTAL2 KROW3 CEC_IN KROW4 SDA RSVD1 SCL RSVD0 VFD_STR PSEN VFD_BLK KCOL 001aai276 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 Table 3. Pin description Symbol Pin Type[1] Description VFD_CLK 1 O pulsed HIGH to clock output of the VFD display driver VFD_DAT 2 O data output to the VFD display driver SBY 3 O power control output to the host processor. Operating mode = LOW-level Standby mode = HIGH-level INT 4 O interrupt line to the host processor. Indicates data is available for reading. The polarity of operation is configured using the common configuration register; default is INT_POL bit = 1, active-HIGH CEC_OUT 5 O output to the CEC interface[2] RST_N 6 I external reset input. Holding this input LOW resets the TDA9951. It must be held LOW for a time after power-up when using an 18 MHz crystal[2]. VSS 7 GND ground; 0 V reference XTAL1 8 I input to the oscillator and internal clock generator circuits (18 MHz crystal)[2] XTAL2 9 O output from the oscillator amplifier CEC_IN 10 I input from the CEC interface[2] SDA 11 I/O I2C-bus serial data input/output[2] SCL 12 I I2C-bus serial clock input[2] |
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