SN54BCT8373A, SN74BCT8373A

SCAN TEST DEVICES

WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JULY 1996

9

POST OFFICE BOX 655303

data register description

boundary-scan register

The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each

normal-function input pin and one BSC for each normal-function output pin. The BSR is used 1) to store test

data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output

pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally

at the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The

contents of the BSR may change during Run-Test/Idle as determined by the current instruction. The contents

of the BSR are not changed in Test-Logic-Reset.

The BSR order of scan is from TDI through bits 17 – 0 to TDO. Table 1 shows the BSR bits and their associated

device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

17

LE

15

1D

7

1Q

16

OE

14

2D

6

2Q

–

–

13

3D

5

3Q

–

–

12

4D

4

4Q

–

–

11

5D

3

5Q

–

–

10

6D

2

6Q

–

–

9

7D

1

7Q

–

–

8

8D

0

8Q

boundary-control register

The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction

to implement additional test operations not included in the basic SCOPE

™ instruction set. Such operations

include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in

Figure 3.

TDO

TDI

Bit 0

(LSB)

Bit 1

(MSB)

Figure 3. Boundary-Control Register Order of Scan