Datenblatt-Suchmaschine für elektronische Bauteile |
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SN74ALS232BDW Datenblatt(PDF) 6 Page - Texas Instruments |
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SN74ALS232BDW Datenblatt(HTML) 6 Page - Texas Instruments |
6 / 8 page SN74ALS232B 16 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS251B – FEBRUARY 1989 – REVISED APRIL 1998 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (see Figure 1) MIN NOM MAX UNIT f † Clock frequency LDCK 40 MHz fclock† Clock frequency UNCK 40 MHz RST low 18 LDCK low 15 tw Pulse duration LDCK high 10 ns UNCK low 15 UNCK high 10 t Setup time Data before LDCK ↑ 8 ns tsu Setup time LDCK inactive before RST ↑ 5 ns th Hold time Data after LDCK ↑ 5 ns th Hold time LDCK inactive after RST ↑ 5 ns † The maximum possible clock frequency is 40 MHz. The maximum clock frequency when using a 50% duty cycle is 33.3 MHz. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP‡ MAX MIN MAX UNIT fmax LDCK, UNCK 50 40 MHz t d LDCK ↑ Any Q 14 23 6 30 ns tpd UNCK ↑ Any Q 15 23 6 30 ns tPLH LDCK ↑ EMPTY 13 20 5 25 ns UNCK ↑ EMPTY 15 22 6 27 tPHL RST ↓ EMPTY 15 21 5 26 ns LDCK ↑ FULL 15 22 6 27 tPLH UNCK ↑ FULL 13 20 5 25 ns tPLH RST ↓ FULL 16 23 7 28 ns ten OE ↑ Q 5 12 1 14 ns tdis OE ↓ Q 5 12 1 16 ns ‡ Typical values at VCC – 5 V, TA = 25°C. |
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