SN74LVC161284

19BIT BUS INTERFACE

SCAS583J − NOVEMBER 1996 − REVISED FEBRUARY 2005

1

POST OFFICE BOX 655303

Open-Drain Outputs Eliminate the Need for

Discrete Resistors

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Type) and IEEE Std 1284-II (Level 2 Type)

Electrical Specifications

Layout

Shrink Small-Outline (DL) and Thin-Shrink

Small-Outline (DGG) Packages

description/ordering information

The SN74LVC161284 is designed for 3-V to 3.6-V

operation.

This

device

provides

asynchronous two-way communication between

data buses. The control-function implementation

minimizes external timing requirements.

This device has eight bidirectional bits; data can

flow in the A-to-B direction when DIR is high and

in the B-to-A direction when DIR is low. This

device also has five drivers, which drive the cable

side, and four receivers. The SN74LVC161284

has one receiver dedicated to the HOST LOGIC

line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in

a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive

requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel

peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have

a 1.4-k

Ω integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low

and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even

The SN74LVC161284 is characterized for operation from 0

°C to 70°C.

Copyright

 2005 Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG OR DL PACKAGE

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HD

A9

A10

A11

A12

A13

A1

A2

GND

A3

A4

A5

A6

GND

A7

A8

PERI LOGIC IN

A14

A15

A16

A17

HOST LOGIC OUT

DIR

Y9

Y10

Y11

Y12

Y13

B1

B2

GND

B3

B4

B5

B6

GND

B7

B8

PERI LOGIC OUT

C14

C15

C16

C17

HOST LOGIC IN