SN74SSTL16847

20-BIT SSTL_3 INTERFACE BUFFER

WITH 3-STATE OUTPUTS

SCBS709A – OCTOBER 1997 – REVISED MAY 1998

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

th

tsu

LOAD CIRCUIT

VREF†

VIH‡

VIL§

VREF†

VREF†

VIH‡

VIL§

VIH‡

VIL§

VREF†

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

Output

Waveform 1

(see Note B)

Output

Waveform 2

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VREF†

VREF†

VTT

VIL§

VIL§

VIH‡

VTT

VIH‡

Output

Control

tPLH

tPHL

VREF†

VREF†

VIH‡

VIL§

VREF†

VREF†

VOH

VOL

Input

Output

25

Ω = SSTL_3 Class II

CL = 10 pF or 30 pF

(see Note A)

Test

Point

VTT

VREF†

25

Ω

50

Ω = SSTL_3 Class I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

VIL§

VIH‡

† VREF = 0.45 VDDQ

‡ VIH = VREF+400mV (AC voltage levels)

§ VIL = VREF–400mV (AC voltage levels)

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 1.25 ns/V,

tf ≤ 1.25 ns/V.

D. The outputs are measured one at a time with one transition per measurement.

E. VTT = VREF = VDDQ X 0.45

F. tPLZ and tPHZ are the same as tdis.

G. tPZL and tPZH are the same as ten.

H. tPLH and tPHL are the same as tpd.

Timing

Input

Data

Input

Figure 1. Load Circuit and Voltage Waveforms