Datenblatt-Suchmaschine für elektronische Bauteile |
|
TL16C550BN Datenblatt(PDF) 5 Page - Texas Instruments |
|
TL16C550BN Datenblatt(HTML) 5 Page - Texas Instruments |
5 / 35 page TL16C550B, TL16C550BI ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS136B – JANUARY 1994 – REVISED AUGUST 1996 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL NAME NO. N NO. FN NO. PT I/O DESCRIPTION A0 A1 A2 28 27 26 31 30 29 28 27 26 I Register select. A0 – A2 are used during read and write operations to select the ACE register to read from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS) signal description. ADS 25 28 24 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in the state they are in when the low-to-high transition of ADS occurs. BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clock rate is established by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK. CS0 CS1 CS2 12 13 14 14 15 16 9 10 11 I Chip select. When CS0 = high, CS1 = high, and CS2 = low, these three inputs select the ACE. When any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description. CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem status register. Bit 0 ( ∆CTS) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an interrupt is generated. D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 43 44 45 46 47 2 3 4 I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status information between the ACE and the CPU. DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the modem status register. Bit 3 ( ∆DCD) of the modem status register indicates that this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DCD changes state, an interrupt is generated. DDIS 23 26 22 O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable an external transceiver. DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem status register. Bit 1 ( ∆DSR) of the modem status register indicates this signal has changed states since the last read from the modem status register. If the modem status interrupt is enabled when DSR changes state, an interrupt is generated. DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level. DTR is placed in the inactive state either as a result of a master reset, during loop mode operation, or clearing the DTR bit. INTRPT 30 33 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modem status interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result of a master reset. MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer to Table 2. OUT1 OUT2 34 31 38 35 34 31 O Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the modem control register. RCLK 9 10 5 I Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE. |
Ähnliche Teilenummer - TL16C550BN |
|
Ähnliche Beschreibung - TL16C550BN |
|
|
Link URL |
Privatsphäre und Datenschutz |
ALLDATASHEETDE.COM |
War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |