TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 –MARCH 2000

4

POST OFFICE BOX 655303

detailed description (continued)

GND/AIN(–)

ADC Code

AIN

Charge

Redistribution

DAC

Control

Logic

_

+

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB

LSB

D15–D4

D3–D0

Conversion result (OD11–OD0)

Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero scale code = 000h, Vcode = GND

Full scale code = FFFh, Vcode = VREFP – 1 LSB

pseudo-differential inputs

The TLC2555 operates in pseudo-differential mode. The inverted input is available on terminal 5. It can have

a maximum input ripple of

±0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

TLC2551

data changes on the rising edge of SCLK. This is typically used for a microcontroller with SPI interface,

although it can also be used for a DSP. The microcontroller SPI interface should be programmed for

CPOL=0 (serial clock reference to ground) and CPHA=1 (data is valid on the falling edge of serial clock).

data changes on the rising edge of SCLK. This is typically used for a TMS320 DSP. If the TLC2551 is

attached to a dedicated DSP serial port. CS terminal can be grounded.

TLC2552/5

The CS and FS inputs are accessed via the same pin (pin 1) on the TLC2552 and TLC2555. The cycle is started

by the falling edge transition provided by either a CS (interfacing with a SPI interface microcontroller) signal or

FS (interfacing with a TMS320 DSP) signal. Timing for the TLC2555 is much like the TLC2551, with the

exception of the CS/FS line.